} while ( 1 );
}
-static void cf_check do_mc_get_cpu_info(void *v)
+static void cf_check __maybe_unused do_mc_get_cpu_info(void *v)
{
int cpu = smp_processor_id();
int cindex, cpn;
(r) <= MSR_IA32_MCx_MISC(per_cpu(nr_mce_banks, cpu) - 1) && \
((r) - MSR_IA32_MC0_CTL) % 4) /* excludes MCi_CTL */
-static bool x86_mc_msrinject_verify(struct xen_mc_msrinject *mci)
+static bool __maybe_unused x86_mc_msrinject_verify(struct xen_mc_msrinject *mci)
{
const struct cpuinfo_x86 *c = &cpu_data[mci->mcinj_cpunr];
int i, errs = 0;
return !errs;
}
-static uint64_t x86_mc_hwcr_wren(void)
+static uint64_t __maybe_unused x86_mc_hwcr_wren(void)
{
uint64_t old;
return old;
}
-static void x86_mc_hwcr_wren_restore(uint64_t hwcr)
+static void __maybe_unused x86_mc_hwcr_wren_restore(uint64_t hwcr)
{
if ( !(hwcr & K8_HWCR_MCi_STATUS_WREN) )
wrmsrl(MSR_K8_HWCR, hwcr);
}
-static void cf_check x86_mc_msrinject(void *data)
+static void cf_check __maybe_unused x86_mc_msrinject(void *data)
{
struct xen_mc_msrinject *mci = data;
struct mcinfo_msr *msr;
x86_mc_hwcr_wren_restore(hwcr);
}
-/*ARGSUSED*/
-static void cf_check x86_mc_mceinject(void *data)
+static void cf_check __maybe_unused x86_mc_mceinject(void *data)
{
printk("Simulating #MC on cpu %d\n", smp_processor_id());
__asm__ __volatile__("int $0x12");
}
+#ifdef CONFIG_PV /* do_mca() hypercall is PV-only */
+
#if BITS_PER_LONG == 64
#define ID2COOKIE(id) ((mctelem_cookie_t)(id))
return ret;
}
+#endif /* CONFIG_PV */
+
static int mcinfo_dumped;
static int cf_check x86_mcinfo_dump_panic(mctelem_cookie_t mctc)