+++ /dev/null
-/*
- * Copyright (C) 2009 Andrew Turner
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-#include <sys/param.h>
-#include <sys/systm.h>
-
-#include <arm/samsung/s3c2xx0/s3c2410reg.h>
-#include <arm/samsung/s3c2xx0/s3c2xx0board.h>
-
-extern vm_offset_t s3c2410_uart_vaddr;
-
-long
-board_init(void)
-{
- s3c2410_uart_vaddr = S3C24X0_UART_BASE(0);
-
- return (64 * 1024 * 1024);
-}
-
+++ /dev/null
-# $FreeBSD$
-arm/arm/bus_space_base.c standard
-arm/arm/bus_space_asm_generic.S standard
-arm/arm/bus_space_generic.c standard
-arm/samsung/s3c2xx0/board_ln2410sbc.c optional board_ln2410sbc
-arm/samsung/s3c2xx0/s3c24x0_rtc.c standard
-arm/samsung/s3c2xx0/s3c24x0_machdep.c standard
-arm/samsung/s3c2xx0/s3c24x0.c standard
-arm/samsung/s3c2xx0/s3c24x0_clk.c standard
-arm/samsung/s3c2xx0/uart_bus_s3c2410.c optional uart
-arm/samsung/s3c2xx0/uart_cpu_s3c2410.c optional uart
-arm/samsung/s3c2xx0/uart_dev_s3c2410.c optional uart
-
-dev/usb/controller/ohci_s3c24x0.c optional ohci
+++ /dev/null
-/* $NetBSD: s3c2410reg.h,v 1.6 2004/02/12 03:52:46 bsh Exp $ */
-
-/*-
- * Copyright (c) 2003, 2004 Genetec corporation. All rights reserved.
- * Written by Hiroyuki Bessho for Genetec corporation.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. The name of Genetec corporation may not be used to endorse
- * or promote products derived from this software without specific prior
- * written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP.
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-
-/*
- * Samsung S3C2410X processor is ARM920T based integrated CPU
- *
- * Reference:
- * S3C2410X User's Manual
- */
-#ifndef _ARM_S3C2XX0_S3C2410REG_H_
-#define _ARM_S3C2XX0_S3C2410REG_H_
-
-/* common definitions for S3C2410 and S3C2440 */
-#include <arm/samsung/s3c2xx0/s3c24x0reg.h>
-
-/*
- * Memory Map
- */
-#define S3C2410_BANK_SIZE 0x08000000
-#define S3C2410_BANK_START(n) (S3C2410_BANK_SIZE*(n))
-#define S3C2410_SDRAM_START S3C2410_BANK_START(6)
-
-
-/* interrupt control */
-#define S3C2410_SUBIRQ_MAX (S3C24X0_SUBIRQ_MIN+10)
-
-/* Clock control */
-/* CLKMAN_CLKCON */
-#define S3C2410_CLKCON_SM (1<<0) /* 1=transition to SPECIAL mode */
-/* CLKMAN_CLKDIVN */
-#define S3C2410_CLKDIVN_HDIVN (1<<1) /* hclk=fclk/2 */
-
-/* NAND Flash controller */
-#define S3C2410_NANDFC_SIZE 0x18
-/* NANDFC_NFCONF */
-#define S3C2410_NFCONF_ENABLE (1<<15) /* NAND controller enabled */
-#define S3C2410_NFCONF_ECC (1<<12) /* Initialize ECC decoder/encoder */
-#define S3C2410_NFCONF_FCE (1<<11) /* Flash chip enabled */
-#define S3C2410_NFCONF_TACLS (7<<8) /* CLE and ALE duration */
-#define S3C2410_NFCONF_TWRPH0 (7<<4) /* TWRPH0 duration */
-#define S3C2410_NFCONF_TWRPH1 (7<<0) /* TWRPH1 duration */
-#define S3C2410_NANDFC_NFCMD 0x04 /* command */
-#define S3C2410_NANDFC_NFADDR 0x08 /* address */
-#define S3C2410_NANDFC_NFDATA 0x0c /* data */
-#define S3C2410_NANDFC_NFSTAT 0x10 /* operation status */
-#define S3C2410_NANDFC_NFECC 0x14 /* ecc */
-
-/* MMC/SD */
-/* SDI_CON */
-#define S3C2410_CON_FIFO_RESET (1<<1)
-
-/* GPIO */
-#define S3C2410_GPIO_SIZE 0xb4
-
-/* SD interface */
-#define S3C2410_SDI_SIZE 0x44
-#define DCON_STOP (1<<14) /* Force the transfer to stop */
-#define S3C2410_SDI_DAT 0x3c
-#define S3C2410_SDI_IMSK 0x40 /* Interrupt mask */
-#define S3C2410_SDI_IMASK_ALL 0x3ffdf
-
-/* ADC */
-#define S3C2410_ADC_SIZE 0x14
-
-#endif /* _ARM_S3C2XX0_S3C2410REG_H_ */
+++ /dev/null
-/* $NetBSD: s3c2410var.h,v 1.2 2003/08/29 12:57:50 bsh Exp $ */
-
-/*-
- * Copyright (c) 2003 Genetec corporation. All rights reserved.
- * Written by Hiroyuki Bessho for Genetec corporation.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. The name of Genetec corporation may not be used to endorse
- * or promote products derived from this software without specific prior
- * written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP.
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-#ifndef _ARM_S3C2410VAR_H_
-#define _ARM_S3C2410VAR_H_
-
-#include <arm/samsung/s3c2xx0/s3c24x0var.h>
-
-int s3c2410_sscom_cnattach(bus_space_tag_t, int, int, int, tcflag_t);
-int s3c2410_sscom_kgdb_attach(bus_space_tag_t, int, int, int, tcflag_t);
-void s3c2410_intr_init(struct s3c24x0_softc *);
-void s3c2410_softreset(void);
-
-void s3c2410_mask_subinterrupts(int);
-void s3c2410_unmask_subinterrupts(int);
-
-void *s3c2410_extint_establish(int, int, int, int (*)(void *), void *);
-void s3c2410_setup_extint(int, int);
-#endif /* _ARM_S3C2410VAR_H_ */
+++ /dev/null
-/*-
- * Copyright (C) 2009 Andrew Turner
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-/*
- * Samsung S3C2440X processor is ARM920T based integrated CPU
- *
- * Reference:
- * S3C2440A/S3C2442B User's Manual
- */
-#ifndef _ARM_S3C2XX0_S3C2440REG_H_
-#define _ARM_S3C2XX0_S3C2440REG_H_
-
-/* common definitions for S3C2410 and S3C2440 */
-#include <arm/samsung/s3c2xx0/s3c24x0reg.h>
-
-/*
- * Memory Map
- */
-#define S3C2440_BANK_SIZE 0x08000000
-#define S3C2440_BANK_START(n) (S3C2410_BANK_SIZE*(n))
-#define S3C2440_SDRAM_START S3C2410_BANK_START(6)
-
-
-/* interrupt control */
-#define S3C2440_SUBIRQ_MAX (S3C24X0_SUBIRQ_MIN+10)
-
-/* Clock control */
-/* CLKMAN_CLKCON */
-#define S3C2440_CLKCON_STOP (1<<0) /* 1=transition to STOP mode */
-/* CLKMAN_CLKDIVN */
-#define S3C2440_CLKDIVN_HDIVN (3<<1) /* hclk */
-#define S3C2440_CLKMAN_CAMDIVN 0x18
-#define S3C2440_CAMDIVN_HCLK4_HALF (1<<9)
-#define S3C2440_CAMDIVN_HCLK3_HALF (1<<8)
-
-/* NAND Flash controller */
-#define S3C2440_NANDFC_SIZE 0x40
-
-#define S3C2440_NANDFC_NFCONT 0x04
-#define S3C2440_NFCONT_LOCK_TIGHT (1<<13) /* Lock part of the NAND */
-#define S3C2440_NFCONT_SOFT_LOCK (1<<12) /* Soft lock part of the NAND */
-#define S3C2440_NFCONT_ILLEGAL_ACC_INT (1<<10) /* Illegal access interrupt */
-#define S3C2440_NFCONT_RNB_INT (1<<9) /* RnB transition interrupt */
-#define S3C2440_NFCONT_RNB_TRANS_MODE (1<<8) /* RnB transition mode */
-#define S3C2440_NFCONT_SPARE_ECC_LOCK (1<<6) /* Lock spare ECC generation */
-#define S3C2440_NFCONT_MAIN_ECC_LOCK (1<<5) /* Lock main ECC generation */
-#define S3C2440_NFCONT_INIT_ECC (1<<4) /* Init ECC encoder/decoder */
-#define S3C2440_NFCONT_NCE (1<<1) /* NAND Chip select */
-#define S3C2440_NFCONT_ENABLE (1<<0) /* Enable the controller */
-#define S3C2440_NANDFC_NFCMMD 0x08
-#define S3C2440_NANDFC_NFADDR 0x0c
-#define S3C2440_NANDFC_NFDATA 0x10
-#define S3C2440_NANDFC_NFSTAT 0x20
-
-/* MMC/SD */
-/* SDI_CON */
-#define S3C2440_CON_RESET (1<<8)
-#define S3C2440_CON_CLOCK_TYPE (1<<5)
-/* SDI_FSTA */
-#define S3c2440_FSTA_RESET (1<<16)
-#define S3C2440_FSTA_FAIL_ERROR_MSK (3<<14)
-#define S3C2440_FSTA_FAIL_NONE (0<<14)
-#define S3C2440_FSTA_FAIL_FIFO (1<<14)
-#define S3C2440_FSTA_FAIL_LAST_TRANS (2<<14)
-
-/* GPIO */
-#define S3C2440_GPIO_SIZE 0xd0
-
-/* SD interface */
-#define S3C2410_SDI_SIZE 0x44
-#define DCON_START (1<<14) /* Start the data transfer */
-#define S3C2440_SDI_IMSK 0x3c /* Interrupt mask */
-#define S3C2440_SDI_IMASK_ALL 0x3C7C0
-#define S3C2440_SDI_DAT 0x40
-
-/* ADC */
-#define ADCTSC_UD_SEN (1<<8)
-#define S3C2440_ADC_SIZE 0x18
-
-/* UART */
-#define S3C2440_UFSTAT_TXCOUNT (0x3f << 8)
-#define S3C2440_UFSTAT_RXCOUNT (0x3f << 0)
-
-#endif /* _ARM_S3C2XX0_S3C2440REG_H_ */
+++ /dev/null
-/* $NetBSD: s3c2410.c,v 1.4 2003/08/27 03:46:05 bsh Exp $ */
-
-/*
- * Copyright (c) 2003 Genetec corporation. All rights reserved.
- * Written by Hiroyuki Bessho for Genetec corporation.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. The name of Genetec corporation may not be used to endorse
- * or promote products derived from this software without specific prior
- * written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP.
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/kernel.h>
-#include <sys/reboot.h>
-#include <sys/malloc.h>
-#include <sys/module.h>
-#include <sys/bus.h>
-
-#include <vm/vm.h>
-#include <vm/pmap.h>
-
-#include <machine/armreg.h>
-#include <machine/cpu.h>
-#include <machine/bus.h>
-
-#include <machine/cpufunc.h>
-#include <machine/intr.h>
-#include <arm/samsung/s3c2xx0/s3c2410reg.h>
-#include <arm/samsung/s3c2xx0/s3c2440reg.h>
-#include <arm/samsung/s3c2xx0/s3c24x0var.h>
-#include <sys/rman.h>
-
-#define S3C2XX0_XTAL_CLK 12000000
-
-bus_space_tag_t s3c2xx0_bs_tag;
-
-#define IPL_LEVELS 13
-u_int irqmasks[IPL_LEVELS];
-
-static struct {
- uint32_t idcode;
- const char *name;
- s3c2xx0_cpu cpu;
-} s3c2x0_cpu_id[] = {
- { CHIPID_S3C2410A, "S3C2410A", CPU_S3C2410 },
- { CHIPID_S3C2440A, "S3C2440A", CPU_S3C2440 },
- { CHIPID_S3C2442B, "S3C2442B", CPU_S3C2440 },
-
- { 0, NULL }
-};
-
-static struct {
- const char *name;
- int prio;
- int unit;
- struct {
- int type;
- u_long start;
- u_long count;
- } res[2];
-} s3c24x0_children[] = {
- { "rtc", 0, -1, {
- { SYS_RES_IOPORT, S3C24X0_RTC_PA_BASE, S3C24X0_RTC_SIZE },
- { 0 },
- } },
- { "timer", 0, -1, { { 0 }, } },
- { "uart", 1, 0, {
- { SYS_RES_IRQ, S3C24X0_INT_UART0, 1 },
- { SYS_RES_IOPORT, S3C24X0_UART_PA_BASE(0),
- S3C24X0_UART_BASE(1) - S3C24X0_UART_BASE(0) },
- } },
- { "uart", 1, 1, {
- { SYS_RES_IRQ, S3C24X0_INT_UART1, 1 },
- { SYS_RES_IOPORT, S3C24X0_UART_PA_BASE(1),
- S3C24X0_UART_BASE(2) - S3C24X0_UART_BASE(1) },
- } },
- { "uart", 1, 2, {
- { SYS_RES_IRQ, S3C24X0_INT_UART2, 1 },
- { SYS_RES_IOPORT, S3C24X0_UART_PA_BASE(2),
- S3C24X0_UART_BASE(3) - S3C24X0_UART_BASE(2) },
- } },
- { "ohci", 0, -1, {
- { SYS_RES_IRQ, S3C24X0_INT_USBH, 0 },
- { SYS_RES_IOPORT, S3C24X0_USBHC_PA_BASE, S3C24X0_USBHC_SIZE },
- } },
- { NULL },
-};
-
-
-/* prototypes */
-static device_t s3c24x0_add_child(device_t, int, const char *, int);
-
-static int s3c24x0_probe(device_t);
-static int s3c24x0_attach(device_t);
-static void s3c24x0_identify(driver_t *, device_t);
-static int s3c24x0_setup_intr(device_t, device_t, struct resource *, int,
- driver_filter_t *, driver_intr_t *, void *, void **);
-static int s3c24x0_teardown_intr(device_t, device_t, struct resource *,
- void *);
-static int s3c24x0_config_intr(device_t, int, enum intr_trigger,
- enum intr_polarity);
-static struct resource *s3c24x0_alloc_resource(device_t, device_t, int, int *,
- u_long, u_long, u_long, u_int);
-static int s3c24x0_activate_resource(device_t, device_t, int, int,
- struct resource *);
-static int s3c24x0_release_resource(device_t, device_t, int, int,
- struct resource *);
-static struct resource_list *s3c24x0_get_resource_list(device_t, device_t);
-
-static void s3c24x0_identify_cpu(device_t);
-
-static device_method_t s3c24x0_methods[] = {
- DEVMETHOD(device_probe, s3c24x0_probe),
- DEVMETHOD(device_attach, s3c24x0_attach),
- DEVMETHOD(device_identify, s3c24x0_identify),
- DEVMETHOD(bus_setup_intr, s3c24x0_setup_intr),
- DEVMETHOD(bus_teardown_intr, s3c24x0_teardown_intr),
- DEVMETHOD(bus_config_intr, s3c24x0_config_intr),
- DEVMETHOD(bus_alloc_resource, s3c24x0_alloc_resource),
- DEVMETHOD(bus_activate_resource, s3c24x0_activate_resource),
- DEVMETHOD(bus_release_resource, s3c24x0_release_resource),
- DEVMETHOD(bus_get_resource_list,s3c24x0_get_resource_list),
- DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
- DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
- {0, 0},
-};
-
-static driver_t s3c24x0_driver = {
- "s3c24x0",
- s3c24x0_methods,
- sizeof(struct s3c24x0_softc),
-};
-static devclass_t s3c24x0_devclass;
-
-DRIVER_MODULE(s3c24x0, nexus, s3c24x0_driver, s3c24x0_devclass, 0, 0);
-
-struct s3c2xx0_softc *s3c2xx0_softc = NULL;
-
-static device_t
-s3c24x0_add_child(device_t bus, int prio, const char *name, int unit)
-{
- device_t child;
- struct s3c2xx0_ivar *ivar;
-
- child = device_add_child_ordered(bus, prio, name, unit);
- if (child == NULL)
- return (NULL);
-
- ivar = malloc(sizeof(*ivar), M_DEVBUF, M_NOWAIT | M_ZERO);
- if (ivar == NULL) {
- device_delete_child(bus, child);
- printf("Can't add alloc ivar\n");
- return (NULL);
- }
- device_set_ivars(child, ivar);
- resource_list_init(&ivar->resources);
-
- return (child);
-}
-
-static void
-s3c24x0_enable_ext_intr(unsigned int irq)
-{
- uint32_t reg, value;
- int offset;
-
- if (irq <= 7) {
- reg = GPIO_PFCON;
- offset = irq * 2;
- } else if (irq <= 23) {
- reg = GPIO_PGCON;
- offset = (irq - 8) * 2;
- } else
- return;
-
- /* Make the pin an interrupt source */
- value = bus_space_read_4(s3c2xx0_softc->sc_iot,
- s3c2xx0_softc->sc_gpio_ioh, reg);
- value &= ~(3 << offset);
- value |= 2 << offset;
- bus_space_write_4(s3c2xx0_softc->sc_iot, s3c2xx0_softc->sc_gpio_ioh,
- reg, value);
-}
-
-static int
-s3c24x0_setup_intr(device_t dev, device_t child,
- struct resource *ires, int flags, driver_filter_t *filt,
- driver_intr_t *intr, void *arg, void **cookiep)
-{
- int error, irq;
-
- error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, filt,
- intr, arg, cookiep);
- if (error != 0)
- return (error);
-
- for (irq = rman_get_start(ires); irq <= rman_get_end(ires); irq++) {
- if (irq >= S3C24X0_EXTIRQ_MIN && irq <= S3C24X0_EXTIRQ_MAX) {
- /* Enable the external interrupt pin */
- s3c24x0_enable_ext_intr(irq - S3C24X0_EXTIRQ_MIN);
- }
- }
- return (0);
-}
-
-static int
-s3c24x0_teardown_intr(device_t dev, device_t child, struct resource *res,
- void *cookie)
-{
- return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, res, cookie));
-}
-
-static int
-s3c24x0_config_intr(device_t dev, int irq, enum intr_trigger trig,
- enum intr_polarity pol)
-{
- uint32_t mask, reg, value;
- int offset;
-
- /* Only external interrupts can be configured */
- if (irq < S3C24X0_EXTIRQ_MIN || irq > S3C24X0_EXTIRQ_MAX)
- return (EINVAL);
-
- /* There is no standard trigger or polarity for the bus */
- if (trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM)
- return (EINVAL);
-
- irq -= S3C24X0_EXTIRQ_MIN;
-
- /* Get the bits to set */
- mask = 0;
- if (pol == INTR_POLARITY_LOW) {
- mask = 2;
- } else if (pol == INTR_POLARITY_HIGH) {
- mask = 4;
- }
- if (trig == INTR_TRIGGER_LEVEL) {
- mask >>= 2;
- }
-
- /* Get the register to set */
- if (irq <= 7) {
- reg = GPIO_EXTINT(0);
- offset = irq * 4;
- } else if (irq <= 15) {
- reg = GPIO_EXTINT(1);
- offset = (irq - 8) * 4;
- } else if (irq <= 23) {
- reg = GPIO_EXTINT(2);
- offset = (irq - 16) * 4;
- } else {
- return (EINVAL);
- }
-
- /* Set the new signaling method */
- value = bus_space_read_4(s3c2xx0_softc->sc_iot,
- s3c2xx0_softc->sc_gpio_ioh, reg);
- value &= ~(7 << offset);
- value |= mask << offset;
- bus_space_write_4(s3c2xx0_softc->sc_iot,
- s3c2xx0_softc->sc_gpio_ioh, reg, value);
-
- return (0);
-}
-
-static struct resource *
-s3c24x0_alloc_resource(device_t bus, device_t child, int type, int *rid,
- u_long start, u_long end, u_long count, u_int flags)
-{
- struct resource_list_entry *rle;
- struct s3c2xx0_ivar *ivar = device_get_ivars(child);
- struct resource_list *rl = &ivar->resources;
- struct resource *res = NULL;
-
- if (device_get_parent(child) != bus)
- return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child,
- type, rid, start, end, count, flags));
-
- rle = resource_list_find(rl, type, *rid);
- if (rle != NULL) {
- /* There is a resource list. Use it */
- if (rle->res)
- panic("Resource rid %d type %d already in use", *rid,
- type);
- if (start == 0UL && end == ~0UL) {
- start = rle->start;
- count = ulmax(count, rle->count);
- end = ulmax(rle->end, start + count - 1);
- }
- /*
- * When allocating an irq with children irq's really
- * allocate the children as it is those we are interested
- * in receiving, not the parent.
- */
- if (type == SYS_RES_IRQ && start == end) {
- switch (start) {
- case S3C24X0_INT_ADCTC:
- start = S3C24X0_INT_TC;
- end = S3C24X0_INT_ADC;
- break;
-#ifdef S3C2440_INT_CAM
- case S3C2440_INT_CAM:
- start = S3C2440_INT_CAM_C;
- end = S3C2440_INT_CAM_P;
- break;
-#endif
- default:
- break;
- }
- count = end - start + 1;
- }
- }
-
- switch (type) {
- case SYS_RES_IRQ:
- res = rman_reserve_resource(
- &s3c2xx0_softc->s3c2xx0_irq_rman, start, end,
- count, flags, child);
- break;
-
- case SYS_RES_IOPORT:
- case SYS_RES_MEMORY:
- res = rman_reserve_resource(
- &s3c2xx0_softc->s3c2xx0_mem_rman,
- start, end, count, flags, child);
- if (res == NULL)
- panic("Unable to map address space %#lX-%#lX", start,
- end);
-
- rman_set_bustag(res, s3c2xx0_bs_tag);
- rman_set_bushandle(res, start);
- if (flags & RF_ACTIVE) {
- if (bus_activate_resource(child, type, *rid, res)) {
- rman_release_resource(res);
- return (NULL);
- }
- }
- break;
- }
-
- if (res != NULL) {
- rman_set_rid(res, *rid);
- if (rle != NULL) {
- rle->res = res;
- rle->start = rman_get_start(res);
- rle->end = rman_get_end(res);
- rle->count = count;
- }
- }
-
- return (res);
-}
-
-static int
-s3c24x0_activate_resource(device_t bus, device_t child, int type, int rid,
- struct resource *r)
-{
- bus_space_handle_t p;
- int error;
-
- if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) {
- error = bus_space_map(rman_get_bustag(r),
- rman_get_bushandle(r), rman_get_size(r), 0, &p);
- if (error)
- return (error);
- rman_set_bushandle(r, p);
- }
- return (rman_activate_resource(r));
-}
-
-static int
-s3c24x0_release_resource(device_t bus, device_t child, int type, int rid,
- struct resource *r)
-{
- struct s3c2xx0_ivar *ivar = device_get_ivars(child);
- struct resource_list *rl = &ivar->resources;
- struct resource_list_entry *rle;
-
- if (rl == NULL)
- return (EINVAL);
-
- rle = resource_list_find(rl, type, rid);
- if (rle == NULL)
- return (EINVAL);
-
- rman_release_resource(r);
- rle->res = NULL;
-
- return 0;
-}
-
-static struct resource_list *
-s3c24x0_get_resource_list(device_t dev, device_t child)
-{
- struct s3c2xx0_ivar *ivar;
-
- ivar = device_get_ivars(child);
- return (&(ivar->resources));
-}
-
-void
-s3c24x0_identify(driver_t *driver, device_t parent)
-{
-
- BUS_ADD_CHILD(parent, 0, "s3c24x0", 0);
-}
-
-int
-s3c24x0_probe(device_t dev)
-{
- return (BUS_PROBE_NOWILDCARD);
-}
-
-int
-s3c24x0_attach(device_t dev)
-{
- struct s3c24x0_softc *sc = device_get_softc(dev);
- bus_space_tag_t iot;
- device_t child;
- unsigned int i, j;
- u_long irqmax;
-
- s3c2xx0_bs_tag = arm_base_bs_tag;
- s3c2xx0_softc = &(sc->sc_sx);
- sc->sc_sx.sc_iot = iot = s3c2xx0_bs_tag;
- s3c2xx0_softc->s3c2xx0_irq_rman.rm_type = RMAN_ARRAY;
- s3c2xx0_softc->s3c2xx0_irq_rman.rm_descr = "S3C24X0 IRQs";
- s3c2xx0_softc->s3c2xx0_mem_rman.rm_type = RMAN_ARRAY;
- s3c2xx0_softc->s3c2xx0_mem_rman.rm_descr = "S3C24X0 Device Registers";
- /* Manage the registor memory space */
- if ((rman_init(&s3c2xx0_softc->s3c2xx0_mem_rman) != 0) ||
- (rman_manage_region(&s3c2xx0_softc->s3c2xx0_mem_rman,
- S3C24X0_DEV_VA_OFFSET,
- S3C24X0_DEV_VA_OFFSET + S3C24X0_DEV_VA_SIZE) != 0) ||
- (rman_manage_region(&s3c2xx0_softc->s3c2xx0_mem_rman,
- S3C24X0_DEV_START, S3C24X0_DEV_STOP) != 0))
- panic("s3c24x0_attach: failed to set up register rman");
-
- /* These are needed for things without a proper device to attach to */
- sc->sc_sx.sc_intctl_ioh = S3C24X0_INTCTL_BASE;
- sc->sc_sx.sc_gpio_ioh = S3C24X0_GPIO_BASE;
- sc->sc_sx.sc_clkman_ioh = S3C24X0_CLKMAN_BASE;
- sc->sc_sx.sc_wdt_ioh = S3C24X0_WDT_BASE;
- sc->sc_timer_ioh = S3C24X0_TIMER_BASE;
-
- /*
- * Identify the CPU
- */
- s3c24x0_identify_cpu(dev);
-
- /*
- * Manage the interrupt space.
- * We need to put this after s3c24x0_identify_cpu as the avaliable
- * interrupts change depending on which CPU we have.
- */
- if (sc->sc_sx.sc_cpu == CPU_S3C2410)
- irqmax = S3C2410_SUBIRQ_MAX;
- else
- irqmax = S3C2440_SUBIRQ_MAX;
- if (rman_init(&s3c2xx0_softc->s3c2xx0_irq_rman) != 0 ||
- rman_manage_region(&s3c2xx0_softc->s3c2xx0_irq_rman, 0,
- irqmax) != 0 ||
- rman_manage_region(&s3c2xx0_softc->s3c2xx0_irq_rman,
- S3C24X0_EXTIRQ_MIN, S3C24X0_EXTIRQ_MAX))
- panic("s3c24x0_attach: failed to set up IRQ rman");
-
- /* calculate current clock frequency */
- s3c24x0_clock_freq(&sc->sc_sx);
- device_printf(dev, "fclk %d MHz hclk %d MHz pclk %d MHz\n",
- sc->sc_sx.sc_fclk / 1000000, sc->sc_sx.sc_hclk / 1000000,
- sc->sc_sx.sc_pclk / 1000000);
-
- /*
- * Attach children devices
- */
-
- for (i = 0; s3c24x0_children[i].name != NULL; i++) {
- child = s3c24x0_add_child(dev, s3c24x0_children[i].prio,
- s3c24x0_children[i].name, s3c24x0_children[i].unit);
- for (j = 0; j < sizeof(s3c24x0_children[i].res) /
- sizeof(s3c24x0_children[i].res[0]) &&
- s3c24x0_children[i].res[j].type != 0; j++) {
- bus_set_resource(child,
- s3c24x0_children[i].res[j].type, 0,
- s3c24x0_children[i].res[j].start,
- s3c24x0_children[i].res[j].count);
- }
- }
-
- bus_generic_probe(dev);
- bus_generic_attach(dev);
-
- return (0);
-}
-
-static void
-s3c24x0_identify_cpu(device_t dev)
-{
- struct s3c24x0_softc *sc = device_get_softc(dev);
- uint32_t idcode;
- int i;
-
- idcode = bus_space_read_4(sc->sc_sx.sc_iot, sc->sc_sx.sc_gpio_ioh,
- GPIO_GSTATUS1);
-
- for (i = 0; s3c2x0_cpu_id[i].name != NULL; i++) {
- if (s3c2x0_cpu_id[i].idcode == idcode)
- break;
- }
- if (s3c2x0_cpu_id[i].name == NULL)
- panic("Unknown CPU detected ((Chip ID: %#X)", idcode);
- device_printf(dev, "Found %s CPU (Chip ID: %#X)\n",
- s3c2x0_cpu_id[i].name, idcode);
- sc->sc_sx.sc_cpu = s3c2x0_cpu_id[i].cpu;
-}
-
-/*
- * fill sc_pclk, sc_hclk, sc_fclk from values of clock controller register.
- *
- * s3c24{1,4}0_clock_freq2() is meant to be called from kernel startup routines.
- * s3c24x0_clock_freq() is for after kernel initialization is done.
- *
- * Because they can be called before bus_space is available we need to use
- * volatile pointers rather than bus_space_read.
- */
-void
-s3c2410_clock_freq2(vm_offset_t clkman_base, int *fclk, int *hclk, int *pclk)
-{
- uint32_t pllcon, divn;
- unsigned int mdiv, pdiv, sdiv;
- unsigned int f, h, p;
-
- pllcon = *(volatile uint32_t *)(clkman_base + CLKMAN_MPLLCON);
- divn = *(volatile uint32_t *)(clkman_base + CLKMAN_CLKDIVN);
-
- mdiv = (pllcon & PLLCON_MDIV_MASK) >> PLLCON_MDIV_SHIFT;
- pdiv = (pllcon & PLLCON_PDIV_MASK) >> PLLCON_PDIV_SHIFT;
- sdiv = (pllcon & PLLCON_SDIV_MASK) >> PLLCON_SDIV_SHIFT;
-
- f = ((mdiv + 8) * S3C2XX0_XTAL_CLK) / ((pdiv + 2) * (1 << sdiv));
- h = f;
- if (divn & S3C2410_CLKDIVN_HDIVN)
- h /= 2;
- p = h;
- if (divn & CLKDIVN_PDIVN)
- p /= 2;
-
- if (fclk) *fclk = f;
- if (hclk) *hclk = h;
- if (pclk) *pclk = p;
-}
-
-void
-s3c2440_clock_freq2(vm_offset_t clkman_base, int *fclk, int *hclk, int *pclk)
-{
- uint32_t pllcon, divn, camdivn;
- unsigned int mdiv, pdiv, sdiv;
- unsigned int f, h, p;
-
- pllcon = *(volatile uint32_t *)(clkman_base + CLKMAN_MPLLCON);
- divn = *(volatile uint32_t *)(clkman_base + CLKMAN_CLKDIVN);
- camdivn = *(volatile uint32_t *)(clkman_base + S3C2440_CLKMAN_CAMDIVN);
-
- mdiv = (pllcon & PLLCON_MDIV_MASK) >> PLLCON_MDIV_SHIFT;
- pdiv = (pllcon & PLLCON_PDIV_MASK) >> PLLCON_PDIV_SHIFT;
- sdiv = (pllcon & PLLCON_SDIV_MASK) >> PLLCON_SDIV_SHIFT;
-
- f = (2 * (mdiv + 8) * S3C2XX0_XTAL_CLK) / ((pdiv + 2) * (1 << sdiv));
- h = f;
- switch((divn >> 1) & 3) {
- case 0:
- break;
- case 1:
- h /= 2;
- break;
- case 2:
- if ((camdivn & S3C2440_CAMDIVN_HCLK4_HALF) ==
- S3C2440_CAMDIVN_HCLK4_HALF)
- h /= 8;
- else
- h /= 4;
- break;
- case 3:
- if ((camdivn & S3C2440_CAMDIVN_HCLK3_HALF) ==
- S3C2440_CAMDIVN_HCLK3_HALF)
- h /= 6;
- else
- h /= 3;
- break;
- }
- p = h;
- if (divn & CLKDIVN_PDIVN)
- p /= 2;
-
- if (fclk) *fclk = f;
- if (hclk) *hclk = h;
- if (pclk) *pclk = p;
-}
-
-void
-s3c24x0_clock_freq(struct s3c2xx0_softc *sc)
-{
- vm_offset_t va;
-
- va = sc->sc_clkman_ioh;
- switch(sc->sc_cpu) {
- case CPU_S3C2410:
- s3c2410_clock_freq2(va, &sc->sc_fclk, &sc->sc_hclk,
- &sc->sc_pclk);
- break;
- case CPU_S3C2440:
- s3c2440_clock_freq2(va, &sc->sc_fclk, &sc->sc_hclk,
- &sc->sc_pclk);
- break;
- }
-}
-
-void
-cpu_reset(void)
-{
- (void) disable_interrupts(PSR_I|PSR_F);
-
- bus_space_write_4(s3c2xx0_bs_tag, s3c2xx0_softc->sc_wdt_ioh, WDT_WTCON,
- WTCON_ENABLE | WTCON_CLKSEL_16 | WTCON_ENRST);
- for(;;);
-}
-
-void
-s3c24x0_sleep(int mode __unused)
-{
- int reg;
-
- reg = bus_space_read_4(s3c2xx0_bs_tag, s3c2xx0_softc->sc_clkman_ioh,
- CLKMAN_CLKCON);
- bus_space_write_4(s3c2xx0_bs_tag, s3c2xx0_softc->sc_clkman_ioh,
- CLKMAN_CLKCON, reg | CLKCON_IDLE);
-}
-
-
-int
-arm_get_next_irq(int last __unused)
-{
- uint32_t intpnd;
- int irq, subirq;
-
- if ((irq = bus_space_read_4(s3c2xx0_bs_tag,
- s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTOFFSET)) != 0) {
-
- /* Clear the pending bit */
- intpnd = bus_space_read_4(s3c2xx0_bs_tag,
- s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTPND);
- bus_space_write_4(s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh,
- INTCTL_SRCPND, intpnd);
- bus_space_write_4(s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh,
- INTCTL_INTPND, intpnd);
-
- switch (irq) {
- case S3C24X0_INT_ADCTC:
- case S3C24X0_INT_UART0:
- case S3C24X0_INT_UART1:
- case S3C24X0_INT_UART2:
- /* Find the sub IRQ */
- subirq = 0x7ff;
- subirq &= bus_space_read_4(s3c2xx0_bs_tag,
- s3c2xx0_softc->sc_intctl_ioh, INTCTL_SUBSRCPND);
- subirq &= ~(bus_space_read_4(s3c2xx0_bs_tag,
- s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTSUBMSK));
- if (subirq == 0)
- return (irq);
-
- subirq = ffs(subirq) - 1;
-
- /* Clear the sub irq pending bit */
- bus_space_write_4(s3c2xx0_bs_tag,
- s3c2xx0_softc->sc_intctl_ioh, INTCTL_SUBSRCPND,
- (1 << subirq));
-
- /*
- * Return the parent IRQ for UART
- * as it is all we ever need
- */
- if (subirq <= 8)
- return (irq);
-
- return (S3C24X0_SUBIRQ_MIN + subirq);
-
- case S3C24X0_INT_0:
- case S3C24X0_INT_1:
- case S3C24X0_INT_2:
- case S3C24X0_INT_3:
- /* There is a 1:1 mapping to the IRQ we are handling */
- return S3C24X0_INT_EXT(irq);
-
- case S3C24X0_INT_4_7:
- case S3C24X0_INT_8_23:
- /* Find the external interrupt being called */
- subirq = 0x7fffff;
- subirq &= bus_space_read_4(s3c2xx0_bs_tag,
- s3c2xx0_softc->sc_gpio_ioh, GPIO_EINTPEND);
- subirq &= ~bus_space_read_4(s3c2xx0_bs_tag,
- s3c2xx0_softc->sc_gpio_ioh, GPIO_EINTMASK);
- if (subirq == 0)
- return (irq);
-
- subirq = ffs(subirq) - 1;
-
- /* Clear the external irq pending bit */
- bus_space_write_4(s3c2xx0_bs_tag,
- s3c2xx0_softc->sc_gpio_ioh, GPIO_EINTPEND,
- (1 << subirq));
-
- return S3C24X0_INT_EXT(subirq);
- }
-
- return (irq);
- }
- return (-1);
-}
-
-void
-arm_mask_irq(uintptr_t irq)
-{
- u_int32_t mask;
-
- if (irq >= S3C24X0_INT_EXT(0) && irq <= S3C24X0_INT_EXT(3)) {
- /* External interrupt 0..3 are directly mapped to irq 0..3 */
- irq -= S3C24X0_EXTIRQ_MIN;
- }
- if (irq < S3C24X0_SUBIRQ_MIN) {
- mask = bus_space_read_4(s3c2xx0_bs_tag,
- s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTMSK);
- mask |= (1 << irq);
- bus_space_write_4(s3c2xx0_bs_tag,
- s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTMSK, mask);
- } else if (irq < S3C24X0_EXTIRQ_MIN) {
- mask = bus_space_read_4(s3c2xx0_bs_tag,
- s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTSUBMSK);
- mask |= (1 << (irq - S3C24X0_SUBIRQ_MIN));
- bus_space_write_4(s3c2xx0_bs_tag,
- s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTSUBMSK, mask);
- } else {
- mask = bus_space_read_4(s3c2xx0_bs_tag,
- s3c2xx0_softc->sc_gpio_ioh, GPIO_EINTMASK);
- mask |= (1 << (irq - S3C24X0_EXTIRQ_MIN));
- bus_space_write_4(s3c2xx0_bs_tag,
- s3c2xx0_softc->sc_intctl_ioh, GPIO_EINTMASK, mask);
- }
-}
-
-void
-arm_unmask_irq(uintptr_t irq)
-{
- u_int32_t mask;
-
- if (irq >= S3C24X0_INT_EXT(0) && irq <= S3C24X0_INT_EXT(3)) {
- /* External interrupt 0..3 are directly mapped to irq 0..3 */
- irq -= S3C24X0_EXTIRQ_MIN;
- }
- if (irq < S3C24X0_SUBIRQ_MIN) {
- mask = bus_space_read_4(s3c2xx0_bs_tag,
- s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTMSK);
- mask &= ~(1 << irq);
- bus_space_write_4(s3c2xx0_bs_tag,
- s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTMSK, mask);
- } else if (irq < S3C24X0_EXTIRQ_MIN) {
- mask = bus_space_read_4(s3c2xx0_bs_tag,
- s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTSUBMSK);
- mask &= ~(1 << (irq - S3C24X0_SUBIRQ_MIN));
- bus_space_write_4(s3c2xx0_bs_tag,
- s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTSUBMSK, mask);
- } else {
- mask = bus_space_read_4(s3c2xx0_bs_tag,
- s3c2xx0_softc->sc_gpio_ioh, GPIO_EINTMASK);
- mask &= ~(1 << (irq - S3C24X0_EXTIRQ_MIN));
- bus_space_write_4(s3c2xx0_bs_tag,
- s3c2xx0_softc->sc_intctl_ioh, GPIO_EINTMASK, mask);
- }
-}
+++ /dev/null
-/* $NetBSD: s3c24x0_clk.c,v 1.6 2005/12/24 20:06:52 perry Exp $ */
-
-/*
- * Copyright (c) 2003 Genetec corporation. All rights reserved.
- * Written by Hiroyuki Bessho for Genetec corporation.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. The name of Genetec corporation may not be used to endorse
- * or promote products derived from this software without specific prior
- * written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP.
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/kernel.h>
-#include <sys/module.h>
-#include <sys/time.h>
-#include <sys/bus.h>
-#include <sys/resource.h>
-#include <sys/rman.h>
-#include <sys/timetc.h>
-
-#include <machine/bus.h>
-#include <machine/cpu.h>
-#include <machine/cpufunc.h>
-#include <machine/frame.h>
-#include <machine/resource.h>
-#include <machine/intr.h>
-#include <arm/samsung/s3c2xx0/s3c24x0reg.h>
-#include <arm/samsung/s3c2xx0/s3c24x0var.h>
-
-struct s3c24x0_timer_softc {
- device_t dev;
-} timer_softc;
-
-static unsigned s3c24x0_timer_get_timecount(struct timecounter *tc);
-
-static struct timecounter s3c24x0_timer_timecounter = {
- s3c24x0_timer_get_timecount, /* get_timecount */
- NULL, /* no poll_pps */
- ~0u, /* counter_mask */
- 3686400, /* frequency */
- "s3c24x0 timer", /* name */
- 1000 /* quality */
-};
-
-static int
-s3c24x0_timer_probe(device_t dev)
-{
-
- device_set_desc(dev, "s3c24x0 timer");
- return (0);
-}
-
-static int
-s3c24x0_timer_attach(device_t dev)
-{
- timer_softc.dev = dev;
-
- /* We need to do this here for devices that expect DELAY to work */
- return (0);
-}
-
-static device_method_t s3c24x0_timer_methods[] = {
- DEVMETHOD(device_probe, s3c24x0_timer_probe),
- DEVMETHOD(device_attach, s3c24x0_timer_attach),
- {0, 0},
-};
-
-static driver_t s3c24x0_timer_driver = {
- "timer",
- s3c24x0_timer_methods,
- sizeof(struct s3c24x0_timer_softc),
-};
-static devclass_t s3c24x0_timer_devclass;
-
-DRIVER_MODULE(s3c24x0timer, s3c24x0, s3c24x0_timer_driver,
- s3c24x0_timer_devclass, 0, 0);
-
-#define TIMER_FREQUENCY(pclk) ((pclk)/16) /* divider=1/16 */
-
-static unsigned int timer4_reload_value;
-static unsigned int timer4_prescaler;
-static unsigned int timer4_mseccount;
-static volatile uint32_t s3c24x0_base;
-
-#define usec_to_counter(t) \
- ((timer4_mseccount*(t))/1000)
-
-#define counter_to_usec(c,pclk) \
- (((c)*timer4_prescaler*1000)/(TIMER_FREQUENCY(pclk)/1000))
-
-static inline int
-read_timer(struct s3c24x0_softc *sc)
-{
- int count;
-
- do {
- count = bus_space_read_2(sc->sc_sx.sc_iot, sc->sc_timer_ioh,
- TIMER_TCNTO(4));
- } while ( __predict_false(count > timer4_reload_value) );
-
- return count;
-}
-
-static unsigned
-s3c24x0_timer_get_timecount(struct timecounter *tc)
-{
- struct s3c24x0_softc *sc = (struct s3c24x0_softc *)s3c2xx0_softc;
- int value;
-
- value = bus_space_read_2(sc->sc_sx.sc_iot, sc->sc_timer_ioh,
- TIMER_TCNTO(4));
- return (s3c24x0_base - value);
-}
-
-static int
-clock_intr(void *arg)
-{
- struct trapframe *fp = arg;
-
- atomic_add_32(&s3c24x0_base, timer4_reload_value);
-
- hardclock(TRAPF_USERMODE(fp), TRAPF_PC(fp));
- return (FILTER_HANDLED);
-}
-
-void
-cpu_initclocks(void)
-{
- struct s3c24x0_softc *sc = (struct s3c24x0_softc *)s3c2xx0_softc;
- long tc;
- struct resource *irq;
- int rid = 0;
- void *ihl;
- int err, prescaler;
- int pclk = s3c2xx0_softc->sc_pclk;
- bus_space_tag_t iot = sc->sc_sx.sc_iot;
- bus_space_handle_t ioh = sc->sc_timer_ioh;
- uint32_t reg;
- device_t dev = timer_softc.dev;
-
- /* We have already been initialized */
- if (timer4_reload_value != 0)
- return;
-
-#define time_constant(hz) (TIMER_FREQUENCY(pclk) /(hz)/ prescaler)
-#define calc_time_constant(hz) \
- do { \
- prescaler = 1; \
- do { \
- ++prescaler; \
- tc = time_constant(hz); \
- } while( tc > 65536 ); \
- } while(0)
-
-
- /* Use the channels 4 and 3 for hardclock and statclock, respectively */
-
- /* stop all timers */
- bus_space_write_4(iot, ioh, TIMER_TCON, 0);
-
- /* calc suitable prescaler value */
- calc_time_constant(hz);
-
- timer4_prescaler = prescaler;
- timer4_reload_value = TIMER_FREQUENCY(pclk) / hz / prescaler;
- timer4_mseccount = TIMER_FREQUENCY(pclk)/timer4_prescaler/1000 ;
-
- bus_space_write_4(iot, ioh, TIMER_TCNTB(4),
- ((prescaler - 1) << 16) | (timer4_reload_value - 1));
-
- printf("clock: hz=%d PCLK=%d prescaler=%d tc=%ld\n",
- hz, pclk, prescaler, tc);
-
- irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, S3C24X0_INT_TIMER4,
- S3C24X0_INT_TIMER4, 1, RF_ACTIVE);
- if (!irq)
- panic("Unable to allocate the clock irq handler.\n");
-
- err = bus_setup_intr(dev, irq, INTR_TYPE_CLK,
- clock_intr, NULL, NULL, &ihl);
- if (err != 0)
- panic("Unable to setup the clock irq handler.\n");
-
- /* set prescaler1 */
- reg = bus_space_read_4(iot, ioh, TIMER_TCFG0);
- bus_space_write_4(iot, ioh, TIMER_TCFG0,
- (reg & ~0xff00) | ((prescaler-1) << 8));
-
- /* divider 1/16 for ch #4 */
- reg = bus_space_read_4(iot, ioh, TIMER_TCFG1);
- bus_space_write_4(iot, ioh, TIMER_TCFG1,
- (reg & ~(TCFG1_MUX_MASK(4))) |
- (TCFG1_MUX_DIV16 << TCFG1_MUX_SHIFT(4)) );
-
-
- /* start timers */
- reg = bus_space_read_4(iot, ioh, TIMER_TCON);
- reg &= ~(TCON_MASK(4));
-
- /* load the time constant */
- bus_space_write_4(iot, ioh, TIMER_TCON, reg | TCON_MANUALUPDATE(4));
- /* set auto reload and start */
- bus_space_write_4(iot, ioh, TIMER_TCON, reg |
- TCON_AUTORELOAD(4) | TCON_START(4) );
-
- s3c24x0_timer_timecounter.tc_frequency = TIMER_FREQUENCY(pclk) /
- timer4_prescaler;
- tc_init(&s3c24x0_timer_timecounter);
-}
-
-/*
- * DELAY:
- *
- * Delay for at least N microseconds.
- */
-void
-DELAY(int n)
-{
- struct s3c24x0_softc *sc = (struct s3c24x0_softc *) s3c2xx0_softc;
- int v0, v1, delta;
- u_int ucnt;
-
- if (timer4_reload_value == 0) {
- /* not initialized yet */
- while ( n-- > 0 ){
- int m;
-
- for (m = 0; m < 100; ++m )
- ;
- }
- return;
- }
-
- /* read down counter */
- v0 = read_timer(sc);
-
- ucnt = usec_to_counter(n);
-
- while( ucnt > 0 ) {
- v1 = read_timer(sc);
- delta = v0 - v1;
- if ( delta < 0 )
- delta += timer4_reload_value;
-
- if((u_int)delta < ucnt){
- ucnt -= (u_int)delta;
- v0 = v1;
- }
- else {
- ucnt = 0;
- }
- }
-}
-
-void
-cpu_startprofclock(void)
-{
-}
-
-void
-cpu_stopprofclock(void)
-{
-}
+++ /dev/null
-/*-
- * Copyright (c) 1994-1998 Mark Brinicombe.
- * Copyright (c) 1994 Brini.
- * All rights reserved.
- *
- * This code is derived from software written for Brini by Mark Brinicombe
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * This product includes software developed by Brini.
- * 4. The name of the company nor the name of the author may be used to
- * endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * RiscBSD kernel project
- *
- * machdep.c
- *
- * Machine dependant functions for kernel setup
- *
- * This file needs a lot of work.
- *
- * Created : 17/09/94
- */
-
-#include "opt_ddb.h"
-#include "opt_kstack_pages.h"
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#define _ARM32_BUS_DMA_PRIVATE
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/sysproto.h>
-#include <sys/signalvar.h>
-#include <sys/imgact.h>
-#include <sys/kernel.h>
-#include <sys/ktr.h>
-#include <sys/linker.h>
-#include <sys/lock.h>
-#include <sys/malloc.h>
-#include <sys/mutex.h>
-#include <sys/pcpu.h>
-#include <sys/proc.h>
-#include <sys/ptrace.h>
-#include <sys/cons.h>
-#include <sys/bio.h>
-#include <sys/bus.h>
-#include <sys/buf.h>
-#include <sys/exec.h>
-#include <sys/kdb.h>
-#include <sys/msgbuf.h>
-#include <machine/physmem.h>
-#include <machine/reg.h>
-#include <machine/cpu.h>
-
-#include <vm/vm.h>
-#include <vm/pmap.h>
-#include <vm/vm_object.h>
-#include <vm/vm_page.h>
-#include <vm/vm_map.h>
-#include <machine/devmap.h>
-#include <machine/vmparam.h>
-#include <machine/pcb.h>
-#include <machine/undefined.h>
-#include <machine/machdep.h>
-#include <machine/metadata.h>
-#include <machine/armreg.h>
-#include <machine/bus.h>
-#include <sys/reboot.h>
-
-#include <arm/samsung/s3c2xx0/s3c24x0var.h>
-#include <arm/samsung/s3c2xx0/s3c2410reg.h>
-#include <arm/samsung/s3c2xx0/s3c2xx0board.h>
-
-/* Page table for mapping proc0 zero page */
-#define KERNEL_PT_SYS 0
-#define KERNEL_PT_KERN 1
-#define KERNEL_PT_KERN_NUM 44
-/* L2 table for mapping after kernel */
-#define KERNEL_PT_AFKERNEL KERNEL_PT_KERN + KERNEL_PT_KERN_NUM
-#define KERNEL_PT_AFKERNEL_NUM 5
-
-/* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */
-#define NUM_KERNEL_PTS (KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM)
-
-extern int s3c2410_pclk;
-
-struct pv_addr kernel_pt_table[NUM_KERNEL_PTS];
-
-/* Physical and virtual addresses for some global pages */
-
-struct pv_addr systempage;
-struct pv_addr msgbufpv;
-struct pv_addr irqstack;
-struct pv_addr undstack;
-struct pv_addr abtstack;
-struct pv_addr kernelstack;
-
-#define _A(a) ((a) & ~L1_S_OFFSET)
-#define _S(s) (((s) + L1_S_SIZE - 1) & ~(L1_S_SIZE-1))
-
-/* Static device mappings. */
-static const struct arm_devmap_entry s3c24x0_devmap[] = {
- /*
- * Map the devices we need early on.
- */
- {
- _A(S3C24X0_CLKMAN_BASE),
- _A(S3C24X0_CLKMAN_PA_BASE),
- _S(S3C24X0_CLKMAN_SIZE),
- VM_PROT_READ|VM_PROT_WRITE,
- PTE_DEVICE,
- },
- {
- _A(S3C24X0_GPIO_BASE),
- _A(S3C24X0_GPIO_PA_BASE),
- _S(S3C2410_GPIO_SIZE),
- VM_PROT_READ|VM_PROT_WRITE,
- PTE_DEVICE,
- },
- {
- _A(S3C24X0_INTCTL_BASE),
- _A(S3C24X0_INTCTL_PA_BASE),
- _S(S3C24X0_INTCTL_SIZE),
- VM_PROT_READ|VM_PROT_WRITE,
- PTE_DEVICE,
- },
- {
- _A(S3C24X0_TIMER_BASE),
- _A(S3C24X0_TIMER_PA_BASE),
- _S(S3C24X0_TIMER_SIZE),
- VM_PROT_READ|VM_PROT_WRITE,
- PTE_DEVICE,
- },
- {
- _A(S3C24X0_UART0_BASE),
- _A(S3C24X0_UART0_PA_BASE),
- _S(S3C24X0_UART_PA_BASE(3) - S3C24X0_UART0_PA_BASE),
- VM_PROT_READ|VM_PROT_WRITE,
- PTE_DEVICE,
- },
- {
- _A(S3C24X0_WDT_BASE),
- _A(S3C24X0_WDT_PA_BASE),
- _S(S3C24X0_WDT_SIZE),
- VM_PROT_READ|VM_PROT_WRITE,
- PTE_DEVICE,
- },
- {
- 0,
- 0,
- 0,
- 0,
- 0,
- }
-};
-
-#undef _A
-#undef _S
-
-#define ioreg_read32(a) (*(volatile uint32_t *)(a))
-#define ioreg_write32(a,v) (*(volatile uint32_t *)(a)=(v))
-
-struct arm32_dma_range s3c24x0_range = {
- .dr_sysbase = 0,
- .dr_busbase = 0,
- .dr_len = 0,
-};
-
-struct arm32_dma_range *
-bus_dma_get_range(void)
-{
-
- if (s3c24x0_range.dr_len == 0) {
- s3c24x0_range.dr_sysbase = dump_avail[0];
- s3c24x0_range.dr_busbase = dump_avail[0];
- s3c24x0_range.dr_len = dump_avail[1] - dump_avail[0];
- }
- return (&s3c24x0_range);
-}
-
-int
-bus_dma_get_range_nb(void)
-{
- return (1);
-}
-
-void *
-initarm(struct arm_boot_params *abp)
-{
- struct pv_addr kernel_l1pt;
- int loop;
- u_int l1pagetable;
- vm_offset_t freemempos;
- vm_offset_t afterkern;
- vm_offset_t lastaddr;
-
- int i;
- uint32_t memsize;
-
- boothowto = 0; /* Likely not needed */
- lastaddr = parse_boot_param(abp);
- arm_physmem_kernaddr = abp->abp_physaddr;
- i = 0;
- set_cpufuncs();
- cpufuncs.cf_sleep = s3c24x0_sleep;
-
- pcpu0_init();
-
- /* Do basic tuning, hz etc */
- init_param1();
-
-#define KERNEL_TEXT_BASE (KERNBASE)
- freemempos = (lastaddr + PAGE_MASK) & ~PAGE_MASK;
- /* Define a macro to simplify memory allocation */
-#define valloc_pages(var, np) \
- alloc_pages((var).pv_va, (np)); \
- (var).pv_pa = (var).pv_va + (abp->abp_physaddr - KERNVIRTADDR);
-
-#define alloc_pages(var, np) \
- (var) = freemempos; \
- freemempos += (np * PAGE_SIZE); \
- memset((char *)(var), 0, ((np) * PAGE_SIZE));
-
- while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0)
- freemempos += PAGE_SIZE;
- valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE);
- for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
- if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) {
- valloc_pages(kernel_pt_table[loop],
- L2_TABLE_SIZE / PAGE_SIZE);
- } else {
- kernel_pt_table[loop].pv_va = freemempos -
- (loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) *
- L2_TABLE_SIZE_REAL;
- kernel_pt_table[loop].pv_pa =
- kernel_pt_table[loop].pv_va - KERNVIRTADDR +
- abp->abp_physaddr;
- }
- }
- /*
- * Allocate a page for the system page mapped to V0x00000000
- * This page will just contain the system vectors and can be
- * shared by all processes.
- */
- valloc_pages(systempage, 1);
-
- /* Allocate stacks for all modes */
- valloc_pages(irqstack, IRQ_STACK_SIZE);
- valloc_pages(abtstack, ABT_STACK_SIZE);
- valloc_pages(undstack, UND_STACK_SIZE);
- valloc_pages(kernelstack, kstack_pages);
- valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
- /*
- * Now we start construction of the L1 page table
- * We start by mapping the L2 page tables into the L1.
- * This means that we can replace L1 mappings later on if necessary
- */
- l1pagetable = kernel_l1pt.pv_va;
-
- /* Map the L2 pages tables in the L1 page table */
- pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH,
- &kernel_pt_table[KERNEL_PT_SYS]);
- for (i = 0; i < KERNEL_PT_KERN_NUM; i++)
- pmap_link_l2pt(l1pagetable, KERNBASE + i * L1_S_SIZE,
- &kernel_pt_table[KERNEL_PT_KERN + i]);
- pmap_map_chunk(l1pagetable, KERNBASE, PHYSADDR,
- (((uint32_t)(lastaddr) - KERNBASE) + PAGE_SIZE) & ~(PAGE_SIZE - 1),
- VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
- afterkern = round_page((lastaddr + L1_S_SIZE) & ~(L1_S_SIZE
- - 1));
- for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) {
- pmap_link_l2pt(l1pagetable, afterkern + i * L1_S_SIZE,
- &kernel_pt_table[KERNEL_PT_AFKERNEL + i]);
- }
-
- /* Map the vector page. */
- pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa,
- VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
- /* Map the stack pages */
- pmap_map_chunk(l1pagetable, irqstack.pv_va, irqstack.pv_pa,
- IRQ_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
- pmap_map_chunk(l1pagetable, abtstack.pv_va, abtstack.pv_pa,
- ABT_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
- pmap_map_chunk(l1pagetable, undstack.pv_va, undstack.pv_pa,
- UND_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
- pmap_map_chunk(l1pagetable, kernelstack.pv_va, kernelstack.pv_pa,
- kstack_pages * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
-
- pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa,
- L1_TABLE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
- pmap_map_chunk(l1pagetable, msgbufpv.pv_va, msgbufpv.pv_pa,
- msgbufsize, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
-
-
- for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
- pmap_map_chunk(l1pagetable, kernel_pt_table[loop].pv_va,
- kernel_pt_table[loop].pv_pa, L2_TABLE_SIZE,
- VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
- }
-
- arm_devmap_bootstrap(l1pagetable, s3c24x0_devmap);
-
- cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
- setttb(kernel_l1pt.pv_pa);
- cpu_tlb_flushID();
- cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2));
-
- /*
- * Pages were allocated during the secondary bootstrap for the
- * stacks for different CPU modes.
- * We must now set the r13 registers in the different CPU modes to
- * point to these stacks.
- * Since the ARM stacks use STMFD etc. we must set r13 to the top end
- * of the stack memory.
- */
-
- cpu_control(CPU_CONTROL_MMU_ENABLE, CPU_CONTROL_MMU_ENABLE);
- set_stackptrs(0);
-
- /*
- * We must now clean the cache again....
- * Cleaning may be done by reading new data to displace any
- * dirty data in the cache. This will have happened in setttb()
- * but since we are boot strapping the addresses used for the read
- * may have just been remapped and thus the cache could be out
- * of sync. A re-clean after the switch will cure this.
- * After booting there are no gross relocations of the kernel thus
- * this problem will not occur after initarm().
- */
- cpu_idcache_wbinv_all();
- cpu_setup();
-
- /* Disable all peripheral interrupts */
- ioreg_write32(S3C24X0_INTCTL_BASE + INTCTL_INTMSK, ~0);
- memsize = board_init();
- /* Find pclk for uart */
- switch(ioreg_read32(S3C24X0_GPIO_BASE + GPIO_GSTATUS1) >> 16) {
- case 0x3241:
- s3c2410_clock_freq2(S3C24X0_CLKMAN_BASE, NULL, NULL,
- &s3c2410_pclk);
- break;
- case 0x3244:
- s3c2440_clock_freq2(S3C24X0_CLKMAN_BASE, NULL, NULL,
- &s3c2410_pclk);
- break;
- }
- cninit();
-
- undefined_init();
-
- init_proc0(kernelstack.pv_va);
-
- arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL);
-
- pmap_curmaxkvaddr = afterkern + 0x100000 * (KERNEL_PT_KERN_NUM - 1);
- vm_max_kernel_address = KERNVIRTADDR + 3 * memsize;
- pmap_bootstrap(freemempos, &kernel_l1pt);
- msgbufp = (void*)msgbufpv.pv_va;
- msgbufinit(msgbufp, msgbufsize);
- mutex_init();
-
- /*
- * Add the physical ram we have available.
- *
- * Exclude the kernel, and all the things we allocated which immediately
- * follow the kernel, from the VM allocation pool but not from crash
- * dumps. virtual_avail is a global variable which tracks the kva we've
- * "allocated" while setting up pmaps.
- *
- * Prepare the list of physical memory available to the vm subsystem.
- */
- arm_physmem_hardware_region(PHYSADDR, memsize);
- arm_physmem_exclude_region(abp->abp_physaddr,
- virtual_avail - KERNVIRTADDR, EXFLAG_NOALLOC);
- arm_physmem_init_kernel_globals();
-
- init_param2(physmem);
- kdb_init();
-
- return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP -
- sizeof(struct pcb)));
-}
+++ /dev/null
-/*
- * Copyright (C) 2010 Andrew Turner
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-#include <sys/param.h>
-#include <sys/bus.h>
-#include <sys/time.h>
-#include <sys/clock.h>
-#include <sys/resource.h>
-#include <sys/systm.h>
-#include <sys/rman.h>
-#include <sys/kernel.h>
-#include <sys/module.h>
-
-#include <machine/bus.h>
-
-#include <arm/samsung/s3c2xx0/s3c24x0reg.h>
-
-#include "clock_if.h"
-
-#define YEAR_BASE 2000
-
-struct s3c2xx0_rtc_softc {
- struct resource *mem_res;
-};
-
-static int
-s3c2xx0_rtc_probe(device_t dev)
-{
-
- device_set_desc(dev, "Samsung Integrated RTC");
- return (0);
-}
-
-static int
-s3c2xx0_rtc_attach(device_t dev)
-{
- struct s3c2xx0_rtc_softc *sc;
- int error, rid;
-
- sc = device_get_softc(dev);
- error = 0;
-
- rid = 0;
- sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
- RF_ACTIVE);
- if (sc->mem_res == NULL) {
- error = ENOMEM;
- goto out;
- }
-
- bus_write_1(sc->mem_res, RTC_RTCCON, RTCCON_RTCEN);
- clock_register(dev, 1000000);
-
-out:
- return (error);
-}
-
-static int
-s3c2xx0_rtc_gettime(device_t dev, struct timespec *ts)
-{
- struct s3c2xx0_rtc_softc *sc;
- struct clocktime ct;
-
-#define READ_TIME() do { \
- ct.year = YEAR_BASE + FROMBCD(bus_read_1(sc->mem_res, RTC_BCDYEAR)); \
- ct.mon = FROMBCD(bus_read_1(sc->mem_res, RTC_BCDMON)); \
- ct.dow = FROMBCD(bus_read_1(sc->mem_res, RTC_BCDDAY)); \
- ct.day = FROMBCD(bus_read_1(sc->mem_res, RTC_BCDDATE)); \
- ct.hour = FROMBCD(bus_read_1(sc->mem_res, RTC_BCDHOUR)); \
- ct.min = FROMBCD(bus_read_1(sc->mem_res, RTC_BCDMIN)); \
- ct.sec = FROMBCD(bus_read_1(sc->mem_res, RTC_BCDSEC)); \
-} while (0)
-
- sc = device_get_softc(dev);
-
- ct.nsec = 0;
- READ_TIME();
- /*
- * Check if we could have read incorrect values
- * as the values could have changed.
- */
- if (ct.sec == 0) {
- READ_TIME();
- }
-
- ct.dow = -1;
-
-#undef READ_TIME
- return (clock_ct_to_ts(&ct, ts));
-}
-
-static int
-s3c2xx0_rtc_settime(device_t dev, struct timespec *ts)
-{
- struct s3c2xx0_rtc_softc *sc;
- struct clocktime ct;
-
- sc = device_get_softc(dev);
-
- /* Resolution: 1 sec */
- if (ts->tv_nsec >= 500000000)
- ts->tv_sec++;
- ts->tv_nsec = 0;
- clock_ts_to_ct(ts, &ct);
-
- bus_write_1(sc->mem_res, RTC_BCDSEC, TOBCD(ct.sec));
- bus_write_1(sc->mem_res, RTC_BCDMIN, TOBCD(ct.min));
- bus_write_1(sc->mem_res, RTC_BCDHOUR, TOBCD(ct.hour));
- bus_write_1(sc->mem_res, RTC_BCDDATE, TOBCD(ct.day));
- bus_write_1(sc->mem_res, RTC_BCDDAY, TOBCD(ct.dow));
- bus_write_1(sc->mem_res, RTC_BCDMON, TOBCD(ct.mon));
- bus_write_1(sc->mem_res, RTC_BCDYEAR, TOBCD(ct.year - YEAR_BASE));
-
- return (0);
-}
-
-static device_method_t s3c2xx0_rtc_methods[] = {
- DEVMETHOD(device_probe, s3c2xx0_rtc_probe),
- DEVMETHOD(device_attach, s3c2xx0_rtc_attach),
-
- DEVMETHOD(clock_gettime, s3c2xx0_rtc_gettime),
- DEVMETHOD(clock_settime, s3c2xx0_rtc_settime),
-
- { 0, 0 },
-};
-
-static driver_t s3c2xx0_rtc_driver = {
- "rtc",
- s3c2xx0_rtc_methods,
- sizeof(struct s3c2xx0_rtc_softc),
-};
-static devclass_t s3c2xx0_rtc_devclass;
-
-DRIVER_MODULE(s3c2xx0_rtc, s3c24x0, s3c2xx0_rtc_driver, s3c2xx0_rtc_devclass,
- 0, 0);
-
+++ /dev/null
-/* $NetBSD: s3c24x0reg.h,v 1.7 2004/02/12 03:52:46 bsh Exp $ */
-
-/*-
- * Copyright (c) 2003 Genetec corporation All rights reserved.
- * Written by Hiroyuki Bessho for Genetec corporation.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. The name of Genetec corporation may not be used to endorse
- * or promote products derived from this software without specific prior
- * written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP.
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-
-/*
- * Samsung S3C2410X/2400 processor is ARM920T based integrated CPU
- *
- * Reference:
- * S3C2410X User's Manual
- * S3C2400 User's Manual
- */
-#ifndef _ARM_S3C2XX0_S3C24X0REG_H_
-#define _ARM_S3C2XX0_S3C24X0REG_H_
-
-/* common definitions for S3C2800, S3C2410 and S3C2440 */
-#include <arm/samsung/s3c2xx0/s3c2xx0reg.h>
-
-/*
- * Map the device registers into kernel space.
- *
- * As most devices use less than 1 page of memory reduce
- * the distance between allocations by right shifting
- * S3C24X0_DEV_SHIFT bits. Because the UART takes 3*0x4000
- * bytes the upper limit on S3C24X0_DEV_SHIFT is 4.
- * TODO: Fix the UART code so we can increase this value.
- */
-#define S3C24X0_DEV_START 0x48000000
-#define S3C24X0_DEV_STOP 0x60000000
-#define S3C24X0_DEV_VA_OFFSET 0xD8000000
-#define S3C24X0_DEV_SHIFT 4
-#define S3C24X0_DEV_PA_SIZE (S3C24X0_DEV_STOP - S3C24X0_DEV_START)
-#define S3C24X0_DEV_VA_SIZE (S3C24X0_DEV_PA_SIZE >> S3C24X0_DEV_SHIFT)
-#define S3C24X0_DEV_PA_TO_VA(x) ((x >> S3C24X0_DEV_SHIFT) - S3C24X0_DEV_START + S3C24X0_DEV_VA_OFFSET)
-
-/*
- * Physical address of integrated peripherals
- */
-#define S3C24X0_MEMCTL_PA_BASE 0x48000000 /* memory controller */
-#define S3C24X0_MEMCTL_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_MEMCTL_PA_BASE)
-#define S3C24X0_USBHC_PA_BASE 0x49000000 /* USB Host controller */
-#define S3C24X0_USBHC_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_USBHC_PA_BASE)
-#define S3C24X0_INTCTL_PA_BASE 0x4a000000 /* Interrupt controller */
-#define S3C24X0_INTCTL_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_INTCTL_PA_BASE)
-#define S3C24X0_INTCTL_SIZE 0x20
-#define S3C24X0_DMAC_PA_BASE 0x4b000000
-#define S3C24X0_DMAC_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_DMAC_PA_BASE)
-#define S3C24X0_DMAC_SIZE 0xe4
-#define S3C24X0_CLKMAN_PA_BASE 0x4c000000 /* clock & power management */
-#define S3C24X0_CLKMAN_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_CLKMAN_PA_BASE)
-#define S3C24X0_LCDC_PA_BASE 0x4d000000 /* LCD controller */
-#define S3C24X0_LCDC_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_LCDC_PA_BASE)
-#define S3C24X0_LCDC_SIZE 0x64
-#define S3C24X0_NANDFC_PA_BASE 0x4e000000 /* NAND Flash controller */
-#define S3C24X0_NANDFC_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_NANDFC_PA_BASE)
-#define S3C24X0_UART0_PA_BASE 0x50000000
-#define S3C24X0_UART0_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_UART0_PA_BASE)
-#define S3C24X0_UART_PA_BASE(n) (S3C24X0_UART0_PA_BASE+0x4000*(n))
-#define S3C24X0_UART_BASE(n) (S3C24X0_UART0_BASE+0x4000*(n))
-#define S3C24X0_TIMER_PA_BASE 0x51000000
-#define S3C24X0_TIMER_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_TIMER_PA_BASE)
-#define S3C24X0_USBDC_PA_BASE 0x5200140
-#define S3C24X0_USBDC_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_USBDC_PA_BASE)
-#define S3C24X0_USBDC_SIZE 0x130
-#define S3C24X0_WDT_PA_BASE 0x53000000
-#define S3C24X0_WDT_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_WDT_PA_BASE)
-#define S3C24X0_IIC_PA_BASE 0x54000000
-#define S3C24X0_IIC_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_IIC_PA_BASE)
-#define S3C24X0_IIS_PA_BASE 0x55000000
-#define S3C24X0_IIS_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_IIS_PA_BASE)
-#define S3C24X0_GPIO_PA_BASE 0x56000000
-#define S3C24X0_GPIO_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_GPIO_PA_BASE)
-#define S3C24X0_RTC_PA_BASE 0x57000000
-#define S3C24X0_RTC_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_RTC_PA_BASE)
-#define S3C24X0_RTC_SIZE 0x8C
-#define S3C24X0_ADC_PA_BASE 0x58000000
-#define S3C24X0_ADC_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_ADC_PA_BASE)
-#define S3C24X0_SPI0_PA_BASE 0x59000000
-#define S3C24X0_SPI0_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_SPI0_PA_BASE)
-#define S3C24X0_SPI1_PA_BASE 0x59000020
-#define S3C24X0_SPI1_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_SPI1_PA_BASE)
-#define S3C24X0_SDI_PA_BASE 0x5a000000 /* SD Interface */
-#define S3C24X0_SDI_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_SDI_PA_BASE)
-
-#define S3C24X0_REG_BASE 0x48000000
-#define S3C24X0_REG_SIZE 0x13000000
-
-/* Memory controller */
-#define MEMCTL_BWSCON 0x00 /* Bus width and wait status */
-#define BWSCON_DW0_SHIFT 1 /* bank0 is odd */
-#define BWSCON_BANK_SHIFT(n) (4*(n)) /* for bank 1..7 */
-#define BWSCON_DW_MASK 0x03
-#define BWSCON_DW_8 0
-#define BWSCON_DW_16 1
-#define BWSCON_DW_32 2
-#define BWSCON_WS 0x04 /* WAIT enable for the bank */
-#define BWSCON_ST 0x08 /* SRAM use UB/LB for the bank */
-
-#define MEMCTL_BANKCON0 0x04 /* Boot ROM control */
-#define MEMCTL_BANKCON(n) (0x04+4*(n)) /* BANKn control */
-#define BANKCON_MT_SHIFT 15
-#define BANKCON_MT_ROM (0<<BANKCON_MT_SHIFT)
-#define BANKCON_MT_DRAM (3<<BANKCON_MT_SHIFT)
-#define BANKCON_TACS_SHIFT 13 /* address set-up time to nGCS */
-#define BANKCON_TCOS_SHIFT 11 /* CS set-up to nOE */
-#define BANKCON_TACC_SHIFT 8 /* CS set-up to nOE */
-#define BANKCON_TOCH_SHIFT 6 /* CS hold time from OE */
-#define BANKCON_TCAH_SHIFT 4 /* address hold time from OE */
-#define BANKCON_TACP_SHIFT 2 /* page mode access cycle */
-#define BANKCON_TACP_2 (0<<BANKCON_TACP_SHIFT)
-#define BANKCON_TACP_3 (1<<BANKCON_TACP_SHIFT)
-#define BANKCON_TACP_4 (2<<BANKCON_TACP_SHIFT)
-#define BANKCON_TACP_6 (3<<BANKCON_TACP_SHIFT)
-#define BANKCON_PMC_4 (1<<0)
-#define BANKCON_PMC_8 (2<<0)
-#define BANKCON_PMC_16 (3<<0)
-#define BANKCON_TRCD_SHIFT 2 /* RAS to CAS delay */
-#define BANKCON_TRCD_2 (0<<2)
-#define BANKCON_TRCD_3 (1<<2)
-#define BANKCON_TRCD_4 (2<<2)
-#define BANKCON_SCAN_8 (0<<0) /* Column address number */
-#define BANKCON_SCAN_9 (1<<0)
-#define BANKCON_SCAN_10 (2<<0)
-#define MEMCTL_REFRESH 0x24 /* DRAM?SDRAM Refresh */
-#define REFRESH_REFEN (1<<23)
-#define REFRESH_TREFMD (1<<22) /* 1=self refresh */
-#define REFRESH_TRP_2 (0<<20)
-#define REFRESH_TRP_3 (1<<20)
-#define REFRESH_TRP_4 (2<<20)
-#define REFRESH_TRC_4 (0<<18)
-#define REFRESH_TRC_5 (1<<18)
-#define REFRESH_TRC_6 (2<<18)
-#define REFRESH_TRC_7 (3<<18)
-#define REFRESH_COUNTER_MASK 0x3ff
-#define MEMCTL_BANKSIZE 0x28 /* Flexible Bank size */
-#define MEMCTL_MRSRB6 0x2c /* SDRAM Mode register */
-#define MEMCTL_MRSRB7 0x30
-#define MRSR_CL_SHIFT 4 /* CAS Latency */
-
-#define S3C24X0_MEMCTL_SIZE 0x34
-
-/* USB Host controller */
-#define S3C24X0_USBHC_SIZE 0x5c
-
-/* Interrupt controller */
-#define INTCTL_PRIORITY 0x0c /* IRQ Priority control */
-#define INTCTL_INTPND 0x10 /* Interrupt request status */
-#define INTCTL_INTOFFSET 0x14 /* Interrupt request source */
-#define INTCTL_SUBSRCPND 0x18 /* sub source pending */
-#define INTCTL_INTSUBMSK 0x1c /* sub mask */
-
-/* Interrupt source */
-#define S3C24X0_INT_ADCTC 31 /* ADC (and TC for 2410) */
-#define S3C24X0_INT_RTC 30 /* RTC alarm */
-#define S3C24X0_INT_SPI1 29 /* SPI 1 */
-#define S3C24X0_INT_UART0 28 /* UART0 */
-#define S3C24X0_INT_IIC 27
-#define S3C24X0_INT_USBH 26 /* USB Host */
-#define S3C24X0_INT_USBD 25 /* USB Device */
-#define S3C24X0_INT_UART1 23 /* UART0 (2410 only) */
-#define S3C24X0_INT_SPI0 22 /* SPI 0 */
-#define S3C24X0_INT_SDI 21
-#define S3C24X0_INT_DMA3 20
-#define S3C24X0_INT_DMA2 19
-#define S3C24X0_INT_DMA1 18
-#define S3C24X0_INT_DMA0 17
-#define S3C24X0_INT_LCD 16
-
-#define S3C24X0_INT_UART2 15 /* UART2 int (2410) */
-#define S3C24X0_INT_TIMER4 14
-#define S3C24X0_INT_TIMER3 13
-#define S3C24X0_INT_TIMER2 12
-#define S3C24X0_INT_TIMER1 11
-#define S3C24X0_INT_TIMER0 10
-#define S3C24X0_INT_TIMER(n) (10+(n)) /* timer interrupt [4:0] */
-#define S3C24X0_INT_WDT 9 /* Watch dog timer */
-#define S3C24X0_INT_TICK 8
-#define S3C24X0_INT_BFLT 7 /* Battery fault */
-#define S3C24X0_INT_8_23 5 /* Ext int 8..23 */
-#define S3C24X0_INT_4_7 4 /* Ext int 4..7 */
-#define S3C24X0_INT_3 3
-#define S3C24X0_INT_2 2
-#define S3C24X0_INT_1 1
-#define S3C24X0_INT_0 0
-
-/* 24{1,4}0 has more than 32 interrupt sources. These are sub-sources
- * that are OR-ed into main interrupt sources, and controlled via
- * SUBSRCPND and SUBSRCMSK registers */
-#define S3C24X0_SUBIRQ_MIN 32
-
-/* cascaded to INT_ADCTC */
-#define S3C24X0_INT_ADC (S3C24X0_SUBIRQ_MIN+10) /* AD converter */
-#define S3C24X0_INT_TC (S3C24X0_SUBIRQ_MIN+9) /* Touch screen */
-/* cascaded to INT_UART2 */
-#define S3C24X0_INT_ERR2 (S3C24X0_SUBIRQ_MIN+8) /* UART2 Error */
-#define S3C24X0_INT_TXD2 (S3C24X0_SUBIRQ_MIN+7) /* UART2 Tx */
-#define S3C24X0_INT_RXD2 (S3C24X0_SUBIRQ_MIN+6) /* UART2 Rx */
-/* cascaded to INT_UART1 */
-#define S3C24X0_INT_ERR1 (S3C24X0_SUBIRQ_MIN+5) /* UART1 Error */
-#define S3C24X0_INT_TXD1 (S3C24X0_SUBIRQ_MIN+4) /* UART1 Tx */
-#define S3C24X0_INT_RXD1 (S3C24X0_SUBIRQ_MIN+3) /* UART1 Rx */
-/* cascaded to INT_UART0 */
-#define S3C24X0_INT_ERR0 (S3C24X0_SUBIRQ_MIN+2) /* UART0 Error */
-#define S3C24X0_INT_TXD0 (S3C24X0_SUBIRQ_MIN+1) /* UART0 Tx */
-#define S3C24X0_INT_RXD0 (S3C24X0_SUBIRQ_MIN+0) /* UART0 Rx */
-
-/*
- * Support for external interrupts. We use values from 48
- * to allow new CPU's to allocate new subirq's.
- */
-#define S3C24X0_EXTIRQ_MIN 48
-#define S3C24X0_EXTIRQ_COUNT 24
-#define S3C24X0_EXTIRQ_MAX (S3C24X0_EXTIRQ_MIN + S3C24X0_EXTIRQ_COUNT - 1)
-#define S3C24X0_INT_EXT(n) (S3C24X0_EXTIRQ_MIN + (n))
-
-/* DMA controller */
-/* XXX */
-
-/* Clock & power manager */
-#define CLKMAN_LOCKTIME 0x00 /* PLL lock time */
-#define CLKMAN_MPLLCON 0x04 /* MPLL control */
-#define CLKMAN_UPLLCON 0x08 /* UPLL control */
-#define PLLCON_MDIV_SHIFT 12
-#define PLLCON_MDIV_MASK (0xff<<PLLCON_MDIV_SHIFT)
-#define PLLCON_PDIV_SHIFT 4
-#define PLLCON_PDIV_MASK (0x3f<<PLLCON_PDIV_SHIFT)
-#define PLLCON_SDIV_SHIFT 0
-#define PLLCON_SDIV_MASK (0x03<<PLLCON_SDIV_SHIFT)
-#define CLKMAN_CLKCON 0x0c
-#define CLKCON_SPI (1<<18)
-#define CLKCON_IIS (1<<17)
-#define CLKCON_IIC (1<<16)
-#define CLKCON_ADC (1<<15)
-#define CLKCON_RTC (1<<14)
-#define CLKCON_GPIO (1<<13)
-#define CLKCON_UART2 (1<<12)
-#define CLKCON_UART1 (1<<11)
-#define CLKCON_UART0 (1<<10) /* PCLK to UART0 */
-#define CLKCON_SDI (1<<9)
-#define CLKCON_TIMER (1<<8) /* PCLK to TIMER */
-#define CLKCON_USBD (1<<7) /* PCLK to USB device controller */
-#define CLKCON_USBH (1<<6) /* PCLK to USB host controller */
-#define CLKCON_LCDC (1<<5) /* PCLK to LCD controller */
-#define CLKCON_NANDFC (1<<4) /* PCLK to NAND Flash controller */
-#define CLKCON_IDLE (1<<2) /* 1=transition to IDLE mode */
-#define CLKMAN_CLKSLOW 0x10
-#define CLKMAN_CLKDIVN 0x14
-#define CLKDIVN_PDIVN (1<<0) /* pclk=hclk/2 */
-
-#define CLKMAN_CLKSLOW 0x10 /* slow clock controll */
-#define CLKSLOW_UCLK (1<<7) /* 1=UPLL off */
-#define CLKSLOW_MPLL (1<<5) /* 1=PLL off */
-#define CLKSLOW_SLOW (1<<4) /* 1: Enable SLOW mode */
-#define CLKSLOW_VAL_MASK 0x0f /* divider value for slow clock */
-
-#define CLKMAN_CLKDIVN 0x14 /* Software reset control */
-#define CLKDIVN_PDIVN (1<<0)
-
-#define S3C24X0_CLKMAN_SIZE 0x18
-
-/* LCD controller */
-#define LCDC_LCDCON1 0x00 /* control 1 */
-#define LCDCON1_ENVID (1<<0) /* enable video */
-#define LCDCON1_BPPMODE_SHIFT 1
-#define LCDCON1_BPPMODE_MASK (0x0f<<LCDCON1_BPPMODE_SHIFT)
-#define LCDCON1_BPPMODE_STN1 (0x0<<LCDCON1_BPPMODE_SHIFT)
-#define LCDCON1_BPPMODE_STN2 (0x1<<LCDCON1_BPPMODE_SHIFT)
-#define LCDCON1_BPPMODE_STN4 (0x2<<LCDCON1_BPPMODE_SHIFT)
-#define LCDCON1_BPPMODE_STN8 (0x3<<LCDCON1_BPPMODE_SHIFT)
-#define LCDCON1_BPPMODE_STN12 (0x4<<LCDCON1_BPPMODE_SHIFT)
-#define LCDCON1_BPPMODE_TFT1 (0x8<<LCDCON1_BPPMODE_SHIFT)
-#define LCDCON1_BPPMODE_TFT2 (0x9<<LCDCON1_BPPMODE_SHIFT)
-#define LCDCON1_BPPMODE_TFT4 (0xa<<LCDCON1_BPPMODE_SHIFT)
-#define LCDCON1_BPPMODE_TFT8 (0xb<<LCDCON1_BPPMODE_SHIFT)
-#define LCDCON1_BPPMODE_TFT16 (0xc<<LCDCON1_BPPMODE_SHIFT)
-#define LCDCON1_BPPMODE_TFT24 (0xd<<LCDCON1_BPPMODE_SHIFT)
-#define LCDCON1_BPPMODE_TFTX (0x8<<LCDCON1_BPPMODE_SHIFT)
-
-#define LCDCON1_PNRMODE_SHIFT 5
-#define LCDCON1_PNRMODE_MASK (0x3<<LCDCON1_PNRMODE_SHIFT)
-#define LCDCON1_PNRMODE_DUALSTN4 (0x0<<LCDCON1_PNRMODE_SHIFT)
-#define LCDCON1_PNRMODE_SINGLESTN4 (0x1<<LCDCON1_PNRMODE_SHIFT)
-#define LCDCON1_PNRMODE_SINGLESTN8 (0x2<<LCDCON1_PNRMODE_SHIFT)
-#define LCDCON1_PNRMODE_TFT (0x3<<LCDCON1_PNRMODE_SHIFT)
-
-#define LCDCON1_MMODE (1<<7) /* VM toggle rate */
-#define LCDCON1_CLKVAL_SHIFT 8
-#define LCDCON1_CLKVAL_MASK (0x3ff<<LCDCON1_CLKVAL_SHIFT)
-#define LCDCON1_LINCNT_SHIFT 18
-#define LCDCON1_LINCNT_MASK (0x3ff<<LCDCON1_LINCNT_SHIFT)
-
-#define LCDC_LCDCON2 0x04 /* control 2 */
-#define LCDCON2_VPSW_SHIFT 0 /* TFT Vsync pulse width */
-#define LCDCON2_VPSW_MASK (0x3f<<LCDCON2_VPSW_SHIFT)
-#define LCDCON2_VFPD_SHIFT 6 /* TFT V front porch */
-#define LCDCON2_VFPD_MASK (0xff<<LCDCON2_VFPD_SHIFT)
-#define LCDCON2_LINEVAL_SHIFT 14 /* Vertical size */
-#define LCDCON2_LINEVAL_MASK (0x3ff<<LCDCON2_LINEVAL_SHIFT)
-#define LCDCON2_VBPD_SHIFT 24 /* TFT V back porch */
-#define LCDCON2_VBPD_MASK (0xff<<LCDCON2_VBPD_SHIFT)
-
-#define LCDC_LCDCON3 0x08 /* control 2 */
-#define LCDCON3_HFPD_SHIFT 0 /* TFT H front porch */
-#define LCDCON3_HFPD_MASK (0xff<<LCDCON3_VPFD_SHIFT)
-#define LCDCON3_LINEBLANK_SHIFT 0 /* STN H blank time */
-#define LCDCON3_LINEBLANK_MASK (0xff<<LCDCON3_LINEBLANK_SHIFT)
-#define LCDCON3_HOZVAL_SHIFT 8 /* Horizontal size */
-#define LCDCON3_HOZVAL_MASK (0x7ff<<LCDCON3_HOZVAL_SHIFT)
-#define LCDCON3_HBPD_SHIFT 19 /* TFT H back porch */
-#define LCDCON3_HBPD_MASK (0x7f<<LCDCON3_HPBD_SHIFT)
-#define LCDCON3_WDLY_SHIFT 19 /* STN vline delay */
-#define LCDCON3_WDLY_MASK (0x03<<LCDCON3_WDLY_SHIFT)
-#define LCDCON3_WDLY_16 (0x00<<LCDCON3_WDLY_SHIFT)
-#define LCDCON3_WDLY_32 (0x01<<LCDCON3_WDLY_SHIFT)
-#define LCDCON3_WDLY_64 (0x02<<LCDCON3_WDLY_SHIFT)
-#define LCDCON3_WDLY_128 (0x03<<LCDCON3_WDLY_SHIFT)
-
-#define LCDC_LCDCON4 0x0c /* control 4 */
-#define LCDCON4_HPSW_SHIFT 0 /* TFT Hsync pulse width */
-#define LCDCON4_HPSW_MASK (0xff<<LCDCON4_HPSW_SHIFT)
-#define LCDCON4_WLH_SHIFT 0 /* STN VLINE high width */
-#define LCDCON4_WLH_MASK (0x03<<LCDCON4_WLH_SHIFT)
-#define LCDCON4_WLH_16 (0x00<<LCDCON4_WLH_SHIFT)
-#define LCDCON4_WLH_32 (0x01<<LCDCON4_WLH_SHIFT)
-#define LCDCON4_WLH_64 (0x02<<LCDCON4_WLH_SHIFT)
-#define LCDCON4_WLH_128 (0x03<<LCDCON4_WLH_SHIFT)
-
-#define LCDCON4_MVAL_SHIFT 8 /* STN VM toggle rate */
-#define LCDCON4_MVAL_MASK (0xff<<LCDCON4_MVAL_SHIFT)
-
-#define LCDC_LCDCON5 0x10 /* control 5 */
-#define LCDCON5_HWSWP (1<<0) /* half-word swap */
-#define LCDCON5_BSWP (1<<1) /* byte swap */
-#define LCDCON5_ENLEND (1<<2) /* TFT: enable LEND signal */
-#define LCDCON5_PWREN (1<<3) /* enable PWREN signale */
-#define LCDCON5_INVLEND (1<<4) /* TFT: LEND signal polarity */
-#define LCDCON5_INVPWREN (1<<5) /* PWREN signal polarity */
-#define LCDCON5_INVVDEN (1<<6) /* VDEN signal polarity */
-#define LCDCON5_INVVD (1<<7) /* video data signal polarity */
-#define LCDCON5_INVVFRAME (1<<8) /* VFRAME/VSYNC signal polarity */
-#define LCDCON5_INVVLINE (1<<9) /* VLINE/HSYNC signal polarity */
-#define LCDCON5_INVVCLK (1<<10) /* VCLK signal polarity */
-#define LCDCON5_INVVCLK_RISING LCDCON5_INVVCLK
-#define LCDCON5_INVVCLK_FALLING 0
-#define LCDCON5_FRM565 (1<<11) /* RGB:565 format*/
-#define LCDCON5_FRM555I 0 /* RGBI:5551 format */
-#define LCDCON5_BPP24BL (1<<12) /* bit order for bpp24 */
-
-#define LCDCON5_HSTATUS_SHIFT 17 /* TFT: horizontal status */
-#define LCDCON5_HSTATUS_MASK (0x03<<LCDCON5_HSTATUS_SHIFT)
-#define LCDCON5_HSTATUS_HSYNC (0x00<<LCDCON5_HSTATUS_SHIFT)
-#define LCDCON5_HSTATUS_BACKP (0x01<<LCDCON5_HSTATUS_SHIFT)
-#define LCDCON5_HSTATUS_ACTIVE (0x02<<LCDCON5_HSTATUS_SHIFT)
-#define LCDCON5_HSTATUS_FRONTP (0x03<<LCDCON5_HSTATUS_SHIFT)
-
-#define LCDCON5_VSTATUS_SHIFT 19 /* TFT: vertical status */
-#define LCDCON5_VSTATUS_MASK (0x03<<LCDCON5_VSTATUS_SHIFT)
-#define LCDCON5_VSTATUS_HSYNC (0x00<<LCDCON5_VSTATUS_SHIFT)
-#define LCDCON5_VSTATUS_BACKP (0x01<<LCDCON5_VSTATUS_SHIFT)
-#define LCDCON5_VSTATUS_ACTIVE (0x02<<LCDCON5_VSTATUS_SHIFT)
-#define LCDCON5_VSTATUS_FRONTP (0x03<<LCDCON5_VSTATUS_SHIFT)
-
-#define LCDC_LCDSADDR1 0x14 /* frame buffer start address */
-#define LCDC_LCDSADDR2 0x18
-#define LCDC_LCDSADDR3 0x1c
-#define LCDSADDR3_OFFSIZE_SHIFT 11
-#define LCDSADDR3_PAGEWIDTH_SHIFT 0
-
-#define LCDC_REDLUT 0x20 /* STN: red lookup table */
-#define LCDC_GREENLUT 0x24 /* STN: green lookup table */
-#define LCDC_BLUELUT 0x28 /* STN: blue lookup table */
-#define LCDC_DITHMODE 0x4c /* STN: dithering mode */
-
-#define LCDC_TPAL 0x50 /* TFT: temporary palette */
-#define TPAL_TPALEN (1<<24)
-#define TPAL_RED_SHIFT 16
-#define TPAL_GREEN_SHIFT 8
-#define TPAL_BLUE_SHIFT 0
-
-#define LCDC_LCDINTPND 0x54
-#define LCDC_LCDSRCPND 0x58
-#define LCDC_LCDINTMSK 0x5c
-#define LCDINT_FICNT (1<<0) /* FIFO trigger interrupt pending */
-#define LCDINT_FRSYN (1<<1) /* frame sync interrupt pending */
-#define LCDINT_FIWSEL (1<<2) /* FIFO trigger level: 1=8 words, 0=4 words*/
-
-#define LCDC_LPCSEL 0x60 /* LPC3600 mode */
-#define LPCSEL_LPC_EN (1<<0) /* enable LPC3600 mode */
-#define LPCSEL_RES_SEL (1<<1) /* 1=240x320 0=320x240 */
-#define LPCSEL_MODE_SEL (1<<2)
-#define LPCSEL_CPV_SEL (1<<3)
-
-
-#define LCDC_PALETTE 0x0400
-#define LCDC_PALETTE_SIZE 0x0400
-
-/* NAND Flash controller */
-#define NANDFC_NFCONF 0x00 /* Configuration */
-/* NANDFC_NFSTAT */
-#define NFSTAT_READY (1<<0) /* NAND flash memory ready/busy status */
-
-
-/* MMC/SD */
-#define SDI_CON 0x00
-#define CON_BYTEORDER (1<<4)
-#define CON_SDIO_INTR (1<<3)
-#define CON_READWAIT_EN (1<<2)
-#define CON_CLOCK_EN (1<<0)
-#define SDI_PRE 0x04
-#define SDI_CARG 0x08
-#define SDI_CCON 0x0c
-#define CCON_ABORDCMD (1<<12) /* Abort SDIO CMD12/52 */
-#define CCON_WITHDATA (1<<11) /* CMD with data */
-#define CCON_LONGRSP (1<<10) /* 136 bit response */
-#define CCON_WAITRSP (1<<9) /* Host waits for response */
-#define CCON_CMD_START (1<<8)
-#define CCON_CMDINDEX_MASK (0x7F) /* Command number index */
-#define SDI_CSTA 0x10
-#define CSTA_RSPCRCFAIL (1<<12)
-#define CSTA_CMDSENT (1<<11)
-#define CSTA_CMDTOUT (1<<10)
-#define CSTA_RSPFIN (1<<9)
-/* All the bits to be cleared */
-#define CSTA_ALL_CLEAR (CSTA_RSPCRCFAIL | CSTA_CMDSENT | \
- CSTA_CMDTOUT | CSTA_RSPFIN)
-#define CSTA_ERROR (CSTA_RSPCRCFAIL | CSTA_CMDTOUT)
-#define CSTA_CMDON (1<<8)
-#define SDI_RSP0 0x14
-#define SDI_RSP1 0x18
-#define SDI_RSP2 0x1c
-#define SDI_RSP3 0x20
-#define SDI_DTIMER 0x24
-#define SDI_BSIZE 0x28
-#define SDI_DCON 0x2c
-#define DCON_PRDTYPE (1<<21)
-#define DCON_TARSP (1<<20) /* Transmit after response */
-#define DCON_RACMD (1<<19) /* Receive after command */
-#define DCON_BACMD (1<<18) /* Busy after command */
-#define DCON_BLKMODE (1<<17) /* Stream/Block mode */
-#define DCON_WIDEBUS (1<<16) /* Standard/Wide bus */
-#define DCON_ENDMA (1<<15) /* DMA Enable */
-/* Determine the direction of the data transfer */
-#define DCON_DATA_READY (0<<12) /* No transfer */
-#define DCON_ONLYBUST (1<<12) /* Check if busy */
-#define DCON_DATA_RECEIVE (2<<12) /* Receive data from SD */
-#define DCON_DATA_TRANSMIT (3<<12) /* Send data to SD */
-#define DCON_BLKNUM_MASK (0x7FF) /* Block number */
-#define SDI_DCNT 0x30
-#define SDI_DSTA 0x34
-#define SDI_FSTA 0x38
-#define FSTA_TX_AVAIL (1<<13)
-#define FSTA_RX_AVAIL (1<<12)
-#define FSTA_TX_FIFO_HALF_FULL (1<<11)
-#define FSTA_TX_FIFO_EMPTY (1<<10)
-#define FSTA_RX_FIFO_LAST_DATA (1<<9)
-#define FSTA_RX_FIFO_FULL (1<<8)
-#define FSTA_RX_FIFO_HALF_FULL (1<<7)
-#define FSTA_FIFO_COUNT_MSK (0x7F)
-
-/* Timer */
-#define TIMER_TCFG0 0x00 /* Timer configuration */
-#define TIMER_TCFG1 0x04
-#define TCFG1_MUX_SHIFT(n) (4*(n))
-#define TCFG1_MUX_MASK(n) (0x0f << TCFG1_MUX_SHIFT(n))
-#define TCFG1_MUX_DIV2 0
-#define TCFG1_MUX_DIV4 1
-#define TCFG1_MUX_DIV8 2
-#define TCFG1_MUX_DIV16 3
-#define TCFG1_MUX_EXT 4
-#define TIMER_TCON 0x08 /* control */
-#define TCON_SHIFT(n) (4 * ((n)==0 ? 0 : (n)+1))
-#define TCON_START(n) (1 << TCON_SHIFT(n))
-#define TCON_MANUALUPDATE(n) (1 << (TCON_SHIFT(n) + 1))
-#define TCON_INVERTER(n) (1 << (TCON_SHIFT(n) + 2))
-#define __TCON_AUTORELOAD(n) (1 << (TCON_SHIFT(n) + 3)) /* n=0..3 */
-#define TCON_AUTORELOAD4 (1<<22) /* stupid hardware design */
-#define TCON_AUTORELOAD(n) \
- ((n)==4 ? TCON_AUTORELOAD4 : __TCON_AUTORELOAD(n))
-#define TCON_MASK(n) (0x0f << TCON_SHIFT(n))
-#define TIMER_TCNTB(n) (0x0c+0x0c*(n)) /* count buffer */
-#define TIMER_TCMPB(n) (0x10+0x0c*(n)) /* compare buffer */
-#define __TIMER_TCNTO(n) (0x14+0x0c*(n)) /* count observation */
-#define TIMER_TCNTO4 0x40
-#define TIMER_TCNTO(n) ((n)==4 ? TIMER_TCNTO4 : __TIMER_TCNTO(n))
-
-#define S3C24X0_TIMER_SIZE 0x44
-
-/* UART */
-/* diffs to s3c2800 */
-/* SSCOM_UMCON */
-#define UMCON_AFC (1<<4) /* auto flow control */
-/* SSCOM_UMSTAT */
-#define UMSTAT_DCTS (1<<2) /* CTS change */
-/* SSCOM_UMSTAT */
-#define ULCON_IR (1<<6)
-#define ULCON_PARITY_SHIFT 3
-
-#define S3C24X0_UART_SIZE 0x2c
-
-/* USB device */
-/* XXX */
-
-/* Watch dog timer */
-#define WDT_WTCON 0x00 /* WDT mode */
-#define WTCON_PRESCALE_SHIFT 8
-#define WTCON_PRESCALE (0xff<<WTCON_PRESCALE_SHIFT)
-#define WTCON_ENABLE (1<<5)
-#define WTCON_CLKSEL (3<<3)
-#define WTCON_CLKSEL_16 (0<<3)
-#define WTCON_CLKSEL_32 (1<<3)
-#define WTCON_CLKSEL_64 (2<<3)
-#define WTCON_CLKSEL_128 (3<<3)
-#define WTCON_ENINT (1<<2)
-#define WTCON_ENRST (1<<0)
-
-#define WTCON_WDTSTOP 0
-
-#define WDT_WTDAT 0x04 /* timer data */
-#define WDT_WTCNT 0x08 /* timer count */
-
-#define S3C24X0_WDT_SIZE 0x0c
-
-/* IIC */
-#define S3C24X0_IIC_SIZE 0x0c
-
-
-/* IIS */
-#define S3C24X0_IIS_SIZE 0x14
-
-/* GPIO */
-#define GPIO_PACON 0x00 /* port A configuration */
-#define GPIO_PADAT 0x04 /* port A data */
-
-#define GPIO_PBCON 0x10
-/* These are only used on port B-H on 2410 & B-H,J on 2440 */
-#define PCON_INPUT 0 /* Input port */
-#define PCON_OUTPUT 1 /* Output port */
-#define PCON_ALTFUN 2 /* Alternate function */
-#define PCON_ALTFUN2 3 /* Alternate function */
-#define GPIO_PBDAT 0x14
-/* This is different between 2440 and 2442 (pull up vs pull down): */
-#define GPIO_PBUP 0x18 /* 2410 & 2440 */
-#define GPIO_PBDOWN 0x18 /* 2442 */
-
-#define GPIO_PCCON 0x20
-#define GPIO_PCDAT 0x24
-#define GPIO_PCUP 0x28 /* 2410 & 2440 */
-#define GPIO_PCDOWN 0x28 /* 2442 */
-
-#define GPIO_PDCON 0x30
-#define GPIO_PDDAT 0x34
-#define GPIO_PDUP 0x38 /* 2410 & 2440 */
-#define GPIO_PDDOWN 0x38 /* 2442 */
-
-#define GPIO_PECON 0x40
-#define PECON_INPUT(x) (0<<((x)*2)) /* Pin is used for input */
-#define PECON_OUTPUT(x) (1<<((x)*2)) /* Pin is used for output */
-#define PECON_FUNC_A(x) (2<<((x)*2)) /* Pin is used for function 'A' */
-#define PECON_FUNC_B(x) (3<<((x)*2)) /* Pin is used for function 'B' */
-#define PECON_MASK(x) (3<<((x)*2))
-#define GPIO_PEDAT 0x44
-#define GPIO_PEUP 0x48 /* 2410 & 2440 */
-#define GPIO_PEDOWN 0x48 /* 2442 */
-#define PEUD_ENABLE(x) (~(1<<(x))) /* Enable the pull Up/Down */
-#define PEUD_DISABLE(x) (1<<(x)) /* Disable the pull Up/Down */
-
-#define GPIO_PFCON 0x50
-#define GPIO_PFDAT 0x54
-#define GPIO_PFUP 0x58 /* 2410 & 2440 */
-#define GPIO_PFDOWN 0x58 /* 2442 */
-
-#define GPIO_PGCON 0x60
-#define GPIO_PGDAT 0x64
-#define GPIO_PGUP 0x68 /* 2410 & 2440 */
-#define GPIO_PGDOWN 0x68 /* 2442 */
-
-#define GPIO_PHCON 0x70
-#define GPIO_PHDAT 0x74
-#define GPIO_PHUP 0x78 /* 2410 & 2440 */
-#define GPIO_PHDOWN 0x78 /* 2442 */
-
-#define GPIO_MISCCR 0x80 /* miscellaneous control */
-#define GPIO_DCLKCON 0x84 /* DCLK 0/1 */
-#define GPIO_EXTINT(n) (0x88+4*(n)) /* external int control 0/1/2 */
-#define GPIO_EINTFLT(n) (0x94+4*(n)) /* external int filter control 0..3 */
-#define EXTINTR_LOW 0x00
-#define EXTINTR_HIGH 0x01
-#define EXTINTR_FALLING 0x02
-#define EXTINTR_RISING 0x04
-#define EXTINTR_BOTH 0x06
-#define GPIO_EINTMASK 0xa4
-#define GPIO_EINTPEND 0xa8
-#define GPIO_GSTATUS0 0xac /* external pin status */
-#define GPIO_GSTATUS1 0xb0 /* Chip ID */
-#define CHIPID_S3C2410A 0x32410002
-#define CHIPID_S3C2440A 0x32440001
-#define CHIPID_S3C2442B 0x32440AAB
-#define GPIO_GSTATUS2 0xb4 /* Reset status */
-#define GPIO_GSTATUS3 0xb8
-#define GPIO_GSTATUS4 0xbc
-
-#define GPIO_SET_FUNC(v,port,func) \
- (((v) & ~(3<<(2*(port))))|((func)<<(2*(port))))
-
-/* ADC */
-#define ADC_ADCCON 0x00
-#define ADCCON_ENABLE_START (1<<0)
-#define ADCCON_READ_START (1<<1)
-#define ADCCON_STDBM (1<<2)
-#define ADCCON_SEL_MUX_SHIFT 3
-#define ADCCON_SEL_MUX_MASK (0x7<<ADCCON_SEL_MUX_SHIFT)
-#define ADCCON_PRSCVL_SHIFT 6
-#define ADCCON_PRSCVL_MASK (0xff<<ADCCON_PRSCVL_SHIFT)
-#define ADCCON_PRSCEN (1<<14)
-#define ADCCON_ECFLG (1<<15)
-
-#define ADC_ADCTSC 0x04
-#define ADCTSC_XY_PST 0x03
-#define ADCTSC_AUTO_PST (1<<2)
-#define ADCTSC_PULL_UP (1<<3)
-#define ADCTSC_XP_SEN (1<<4)
-#define ADCTSC_XM_SEN (1<<5)
-#define ADCTSC_YP_SEN (1<<6)
-#define ADCTSC_YM_SEN (1<<7)
-#define ADC_ADCDLY 0x08
-#define ADC_ADCDAT0 0x0c
-#define ADC_ADCDAT1 0x10
-
-#define ADCDAT_DATAMASK 0x3ff
-
-/* RTC */
-#define RTC_RTCCON 0x40
-#define RTCCON_RTCEN (1<<0)
-#define RTCCON_CLKSEL (1<<1)
-#define RTCCON_CNTSEL (1<<2)
-#define RTCCON_CLKRST (1<<3)
-#define RTC_TICNT0 0x44
-/* TICNT1 on 2440 */
-#define RTC_RTCALM 0x50
-#define RTC_ALMSEC 0x54
-#define RTC_ALMMIN 0x58
-#define RTC_ALMHOUR 0x5C
-#define RTC_ALMDATE 0x60
-#define RTC_ALMMON 0x64
-#define RTC_ALMYEAR 0x68
-/* RTCRST on 2410 */
-#define RTC_BCDSEC 0x70
-#define RTC_BCDMIN 0x74
-#define RTC_BCDHOUR 0x78
-#define RTC_BCDDATE 0x7C
-#define RTC_BCDDAY 0x80
-#define RTC_BCDMON 0x84
-#define RTC_BCDYEAR 0x88
-
-
-/* SPI */
-#define S3C24X0_SPI_SIZE 0x20
-
-#define SPI_SPCON 0x00
-#define SPCON_TAGD (1<<0) /* Tx auto garbage */
-#define SPCON_CPHA (1<<1)
-#define SPCON_CPOL (1<<2)
-#define SPCON_IDLELOW_RISING (0|0)
-#define SPCON_IDLELOW_FALLING (0|SPCON_CPHA)
-#define SPCON_IDLEHIGH_FALLING (SPCON_CPOL|0)
-#define SPCON_IDLEHIGH_RISING (SPCON_CPOL|SPCON_CPHA)
-#define SPCON_MSTR (1<<3)
-#define SPCON_ENSCK (1<<4)
-#define SPCON_SMOD_SHIFT 5
-#define SPCON_SMOD_MASK (0x03<<SPCON_SMOD_SHIFT)
-#define SPCON_SMOD_POLL (0x00<<SPCON_SMOD_SHIFT)
-#define SPCON_SMOD_INT (0x01<<SPCON_SMOD_SHIFT)
-#define SPCON_SMOD_DMA (0x02<<SPCON_SMOD_SHIFT)
-
-#define SPI_SPSTA 0x04 /* status register */
-#define SPSTA_REDY (1<<0) /* ready */
-#define SPSTA_MULF (1<<1) /* multi master error */
-#define SPSTA_DCOL (1<<2) /* Data collision error */
-
-#define SPI_SPPIN 0x08
-#define SPPIN_KEEP (1<<0)
-#define SPPIN_ENMUL (1<<2) /* multi master error detect */
-
-#define SPI_SPPRE 0x0c /* prescaler */
-#define SPI_SPTDAT 0x10 /* tx data */
-#define SPI_SPRDAT 0x14 /* rx data */
-
-
-#endif /* _ARM_S3C2XX0_S3C24X0REG_H_ */
+++ /dev/null
-/* $NetBSD: s3c24x0var.h,v 1.1 2003/07/31 19:49:44 bsh Exp $ */
-
-/*-
- * Copyright (c) 2003 Genetec corporation. All rights reserved.
- * Written by Hiroyuki Bessho for Genetec corporation.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. The name of Genetec corporation may not be used to endorse
- * or promote products derived from this software without specific prior
- * written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP.
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-#ifndef _ARM_S3C24X0VAR_H_
-#define _ARM_S3C24X0VAR_H_
-
-#include <arm/samsung/s3c2xx0/s3c2xx0var.h>
-
-struct s3c24x0_softc {
- struct s3c2xx0_softc sc_sx;
-
- bus_space_handle_t sc_timer_ioh; /* Timer control registers */
-};
-
-void s3c24x0_clock_freq(struct s3c2xx0_softc *);
-void s3c2410_clock_freq2(vm_offset_t, int *, int *, int *);
-void s3c2440_clock_freq2(vm_offset_t, int *, int *, int *);
-
-void s3c24x0_sleep(int);
-
-#endif /* _ARM_S3C24X0VAR_H_ */
+++ /dev/null
-/*-
- * Copyright (c) 2008 Warner Losh. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-/* $FreeBSD$ */
-
-#ifndef _ARM_S3C2XX0_S3C2XX0BOARD_H_
-#define _ARM_S3C2XX0_S3C2XX0BOARD_H_
-
-/*
- * These routines are expected to be provided by the board files.
- */
-long board_init(void);
-
-#endif /* _ARM_S3C2XX0_S3C2XX0BOARD_H_ */
+++ /dev/null
-/* $NetBSD: s3c2xx0reg.h,v 1.4 2004/02/12 03:47:29 bsh Exp $ */
-
-/*-
- * Copyright (c) 2002, 2003 Fujitsu Component Limited
- * Copyright (c) 2002, 2003 Genetec Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of The Fujitsu Component Limited nor the name of
- * Genetec corporation may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC
- * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
- * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC
- * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-
-/*
- * Register definitions common to S3C2800 and S3C24[01]0
- */
-#ifndef _ARM_S3C2XX0_S3C2XX0REG_H_
-#define _ARM_S3C2XX0_S3C2XX0REG_H_
-
-/* UART */
-/*
- * S3C2800, 2410 and 2400 have a common built-in UART block. However,
- * there are small diffs in bit position of some registers.
- * Following definitions can be foune in s3c{2800,24x0}reg.h for
- * that reason.
- *
- * ULCON_IR (Infra-red mode)
- * ULCON_PARITY_SHIFT (Parity mode bit position)
- * UMCON_AFC (Auto flow control)
- * UMSTAT_DCTS (CTS change)
- */
-
-#define SSCOM_ULCON 0x00 /* UART line control */
-/* ULCON_PARITY_SHIFT and ULCON_IR is defined in s3c{2800,24x0}reg.h */
-#define ULCON_PARITY_NONE (0<<ULCON_PARITY_SHIFT)
-#define ULCON_PARITY_ODD (4<<ULCON_PARITY_SHIFT)
-#define ULCON_PARITY_EVEN (5<<ULCON_PARITY_SHIFT)
-#define ULCON_PARITY_ONE (6<<ULCON_PARITY_SHIFT)
-#define ULCON_PARITY_ZERO (7<<ULCON_PARITY_SHIFT)
-#define ULCON_STOP (1<<2)
-#define ULCON_LENGTH_5 0
-#define ULCON_LENGTH_6 1
-#define ULCON_LENGTH_7 2
-#define ULCON_LENGTH_8 3
-#define SSCOM_UCON 0x04 /* UART control */
-#define UCON_TXINT_TYPE (1<<9) /* Tx interrupt. 0=pulse,1=level */
-#define UCON_TXINT_TYPE_LEVEL UCON_TXINT_TYPE
-#define UCON_TXINT_TYPE_PULSE 0
-#define UCON_RXINT_TYPE (1<<8) /* Rx interrupt */
-#define UCON_RXINT_TYPE_LEVEL UCON_RXINT_TYPE
-#define UCON_RXINT_TYPE_PULSE 0
-#define UCON_TOINT (1<<7) /* Rx timeout interrupt */
-#define UCON_ERRINT (1<<6) /* receive error interrupt */
-#define UCON_LOOP (1<<5) /* loopback */
-#define UCON_SBREAK (1<<4) /* send break */
-#define UCON_TXMODE_DISABLE (0<<2)
-#define UCON_TXMODE_INT (1<<2)
-#define UCON_TXMODE_DMA (2<<2)
-#define UCON_TXMODE_MASK (3<<2)
-#define UCON_RXMODE_DISABLE (0<<0)
-#define UCON_RXMODE_INT (1<<0)
-#define UCON_RXMODE_DMA (2<<0)
-#define UCON_RXMODE_MASK (3<<0)
-#define SSCOM_UFCON 0x08 /* FIFO control */
-#define UFCON_TXTRIGGER_0 (0<<6)
-#define UFCON_TXTRIGGER_4 (1<<6)
-#define UFCON_TXTRIGGER_8 (2<<6)
-#define UFCON_TXTRIGGER_16 (3<<6)
-#define UFCON_RXTRIGGER_4 (0<<4)
-#define UFCON_RXTRIGGER_8 (1<<4)
-#define UFCON_RXTRIGGER_12 (2<<4)
-#define UFCON_RXTRIGGER_16 (3<<4)
-#define UFCON_TXFIFO_RESET (1<<2)
-#define UFCON_RXFIFO_RESET (1<<1)
-#define UFCON_FIFO_ENABLE (1<<0)
-#define SSCOM_UMCON 0x0c /* MODEM control */
-/* UMCON_AFC is defined in s3c{2800,24x0}reg.h */
-#define UMCON_RTS (1<<0) /* Request to send */
-#define SSCOM_UTRSTAT 0x10 /* Status register */
-#define UTRSTAT_TXSHIFTER_EMPTY (1<<2)
-#define UTRSTAT_TXEMPTY (1<<1) /* TX fifo or buffer empty */
-#define UTRSTAT_RXREADY (1<<0) /* RX fifo or buffer is not empty */
-#define SSCOM_UERSTAT 0x14 /* Error status register */
-#define UERSTAT_BREAK (1<<3) /* Break signal, not 2410 */
-#define UERSTAT_FRAME (1<<2) /* Frame error */
-#define UERSTAT_PARITY (1<<1) /* Parity error, not 2410 */
-#define UERSTAT_OVERRUN (1<<0) /* Overrun */
-#define UERSTAT_ALL_ERRORS \
- (UERSTAT_OVERRUN|UERSTAT_BREAK|UERSTAT_FRAME|UERSTAT_PARITY)
-#define SSCOM_UFSTAT 0x18 /* Fifo status register */
-#define UFSTAT_TXFULL (1<<9) /* Tx fifo full */
-#define UFSTAT_RXFULL (1<<8) /* Rx fifo full */
-#define UFSTAT_TXCOUNT_SHIFT 4 /* TX FIFO count */
-#define UFSTAT_TXCOUNT (0x0f<<UFSTAT_TXCOUNT_SHIFT)
-#define UFSTAT_RXCOUNT_SHIFT 0 /* RX FIFO count */
-#define UFSTAT_RXCOUNT (0x0f<<UFSTAT_RXCOUNT_SHIFT)
-#define SSCOM_UMSTAT 0x1c /* Modem status register */
-/* UMSTAT_DCTS is defined in s3c{2800,24x0}reg.h */
-#define UMSTAT_CTS (1<<0) /* Clear to send */
-#if _BYTE_ORDER == _LITTLE_ENDIAN
-#define SSCOM_UTXH 0x20 /* Transmit data register */
-#define SSCOM_URXH 0x24 /* Receive data register */
-#else
-#define SSCOM_UTXH 0x23 /* Transmit data register */
-#define SSCOM_URXH 0x27 /* Receive data register */
-#endif
-#define SSCOM_UBRDIV 0x28 /* baud-reate divisor */
-#define SSCOM_SIZE 0x2c
-
-/* Interrupt controller (Common to S3c2800/2400X/2410X) */
-#define INTCTL_SRCPND 0x00 /* Interrupt request status */
-#define INTCTL_INTMOD 0x04 /* Interrupt mode (FIQ/IRQ) */
-#define INTCTL_INTMSK 0x08 /* Interrupt mask */
-
-#endif /* _ARM_S3C2XX0_S3C2XX0REG_H_ */
+++ /dev/null
-/* $NetBSD: s3c2xx0var.h,v 1.3 2003/08/05 11:26:54 bsh Exp $ */
-
-/*-
- * Copyright (c) 2002 Fujitsu Component Limited
- * Copyright (c) 2002 Genetec Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of The Fujitsu Component Limited nor the name of
- * Genetec corporation may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC
- * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
- * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC
- * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-#ifndef _ARM_S3C2XX0VAR_H_
-#define _ARM_S3C2XX0VAR_H_
-
-#include <machine/bus.h>
-#include <sys/rman.h>
-
-typedef enum {
- CPU_S3C2410,
- CPU_S3C2440,
-} s3c2xx0_cpu;
-
-struct s3c2xx0_softc {
- device_t sc_dev;
-
- s3c2xx0_cpu sc_cpu;
-
- bus_space_tag_t sc_iot;
-
- bus_space_handle_t sc_intctl_ioh;
- bus_space_handle_t sc_gpio_ioh; /* GPIO */
- bus_space_handle_t sc_clkman_ioh; /* Clock manager */
- bus_space_handle_t sc_wdt_ioh; /* Watchdog Timer */
-
- bus_dma_tag_t sc_dmat;
-
- /* clock frequency */
- int sc_fclk; /* CPU clock */
- int sc_hclk; /* AHB bus clock */
- int sc_pclk; /* peripheral clock */
-
- struct rman s3c2xx0_irq_rman;
- struct rman s3c2xx0_mem_rman;
-};
-
-struct s3c2xx0_ivar {
- struct resource_list resources;
-};
-
-typedef void *s3c2xx0_chipset_tag_t;
-
-extern bus_space_tag_t s3c2xx0_bs_tag;
-extern struct s3c2xx0_softc *s3c2xx0_softc;
-extern struct arm32_bus_dma_tag s3c2xx0_bus_dma;
-
-/* Platform needs to provide this */
-bus_dma_tag_t s3c2xx0_bus_dma_init(struct arm32_bus_dma_tag *);
-
-#endif /* _ARM_S3C2XX0VAR_H_ */
+++ /dev/null
-#$FreeBSD$
-include "../samsung/s3c2xx0/std.s3c2410"
-
-makeoptions KERNPHYSADDR=0x30000000
-makeoptions KERNVIRTADDR=0xc0000000
-options KERNPHYSADDR=0x30000000
-options KERNVIRTADDR=0xc0000000
-options PHYSADDR=0x30000000
-options NO_EVENTTIMERS
-
+++ /dev/null
-# $FreeBSD$
-
-files "../samsung/s3c2xx0/files.s3c2xx0"
-cpu CPU_ARM9
-machine arm
-
-makeoptions CONF_CFLAGS=-mcpu=arm920t
-options NO_EVENTTIMERS
+++ /dev/null
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/bus.h>
-#include <sys/conf.h>
-#include <sys/kernel.h>
-#include <sys/module.h>
-#include <machine/bus.h>
-#include <sys/rman.h>
-#include <machine/resource.h>
-
-#include <dev/uart/uart.h>
-#include <dev/uart/uart_bus.h>
-#include <dev/uart/uart_cpu.h>
-
-#include <arm/samsung/s3c2xx0/s3c24x0reg.h>
-
-#include "uart_if.h"
-
-extern struct uart_class uart_s3c2410_class;
-
-static int uart_s3c2410_probe(device_t dev);
-
-static device_method_t uart_s3c2410_methods[] = {
- /* Device interface */
- DEVMETHOD(device_probe, uart_s3c2410_probe),
- DEVMETHOD(device_attach, uart_bus_attach),
- DEVMETHOD(device_detach, uart_bus_detach),
- { 0, 0 }
-};
-
-static driver_t uart_s3c2410_driver = {
- uart_driver_name,
- uart_s3c2410_methods,
- sizeof(struct uart_softc),
-};
-
-extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
-static int
-uart_s3c2410_probe(device_t dev)
-{
- struct uart_devinfo *sysdev;
- struct uart_softc *sc;
- int unit;
-
- sc = device_get_softc(dev);
- sc->sc_class = &uart_s3c2410_class;
-
- unit = device_get_unit(dev);
- sysdev = SLIST_FIRST(&uart_sysdevs);
- if (S3C24X0_UART_BASE(unit) == sysdev->bas.bsh) {
- sc->sc_sysdev = sysdev;
- bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas));
- }
- return(uart_bus_probe(dev, 0, 0, 0, unit));
-}
-
-DRIVER_MODULE(uart, s3c24x0, uart_s3c2410_driver, uart_devclass, 0, 0);
+++ /dev/null
-/*
- * Copyright (c) 2003 Marcel Moolenaar
- * Copyright (c) 2007 Andrew Turner
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/bus.h>
-#include <sys/cons.h>
-#include <machine/bus.h>
-
-#include <dev/uart/uart.h>
-#include <dev/uart/uart_cpu.h>
-
-#include <arm/samsung/s3c2xx0/s3c2xx0var.h>
-
-extern struct uart_class uart_s3c2410_class;
-
-bus_space_tag_t uart_bus_space_io;
-bus_space_tag_t uart_bus_space_mem;
-
-vm_offset_t s3c2410_uart_vaddr;
-unsigned int s3c2410_pclk;
-
-int
-uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2)
-{
- return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0);
-}
-
-int
-uart_cpu_getdev(int devtype, struct uart_devinfo *di)
-{
- if (devtype != UART_DEV_CONSOLE)
- return (ENXIO);
-
- di->ops = uart_getops(&uart_s3c2410_class);
- di->bas.chan = 0;
- di->bas.bst = s3c2xx0_bs_tag;
- di->bas.bsh = s3c2410_uart_vaddr;
- di->bas.regshft = 0;
- di->bas.rclk = s3c2410_pclk;
- di->baudrate = 115200;
- di->databits = 8;
- di->stopbits = 1;
- di->parity = UART_PARITY_NONE;
- uart_bus_space_io = s3c2xx0_bs_tag;
- uart_bus_space_mem = NULL;
-
- return (0);
-}
+++ /dev/null
-/*
- * Copyright (c) 2003 Marcel Moolenaar
- * Copyright (c) 2007-2009 Andrew Turner
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/bus.h>
-#include <sys/conf.h>
-#include <sys/cons.h>
-#include <sys/tty.h>
-#include <sys/rman.h>
-#include <machine/bus.h>
-#include <machine/intr.h>
-
-#include <dev/uart/uart.h>
-#include <dev/uart/uart_cpu.h>
-#include <dev/uart/uart_bus.h>
-#include <arm/samsung/s3c2xx0/s3c2440reg.h>
-#include <arm/samsung/s3c2xx0/uart_dev_s3c2410.h>
-#include <arm/samsung/s3c2xx0/s3c2xx0reg.h>
-#include <arm/samsung/s3c2xx0/s3c2xx0var.h>
-#include "uart_if.h"
-
-/* Finds the subirq from the parent */
-#define get_sub_irq(parent, offset) \
- ((parent == S3C24X0_INT_UART0) ? S3C24X0_SUBIRQ_MIN + offset : \
- ((parent == S3C24X0_INT_UART1) ? S3C24X0_SUBIRQ_MIN + 3 + offset : \
- S3C24X0_SUBIRQ_MIN + 6 + offset))
-#define RX_OFF 0
-#define TX_OFF 1
-#define ERR_OFF 2
-
-extern unsigned int s3c2410_pclk;
-
-static int sscomspeed(long, long);
-static int s3c24x0_uart_param(struct uart_bas *, int, int, int, int);
-
-/*
- * Low-level UART interface.
- */
-static int s3c2410_probe(struct uart_bas *bas);
-static void s3c2410_init(struct uart_bas *bas, int, int, int, int);
-static void s3c2410_term(struct uart_bas *bas);
-static void s3c2410_putc(struct uart_bas *bas, int);
-static int s3c2410_rxready(struct uart_bas *bas);
-static int s3c2410_getc(struct uart_bas *bas, struct mtx *mtx);
-
-extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
-
-static int
-sscomspeed(long speed, long frequency)
-{
- int x;
-
- if (speed <= 0 || frequency <= 0)
- return -1;
- x = (frequency / 16) / speed;
- return x-1;
-}
-
-static int
-s3c24x0_uart_param(struct uart_bas *bas, int baudrate, int databits,
- int stopbits, int parity)
-{
- int brd, ulcon;
-
- ulcon = 0;
-
- switch(databits) {
- case 5:
- ulcon |= ULCON_LENGTH_5;
- break;
- case 6:
- ulcon |= ULCON_LENGTH_6;
- break;
- case 7:
- ulcon |= ULCON_LENGTH_7;
- break;
- case 8:
- ulcon |= ULCON_LENGTH_8;
- break;
- default:
- return (EINVAL);
- }
-
- switch (parity) {
- case UART_PARITY_NONE:
- ulcon |= ULCON_PARITY_NONE;
- break;
- case UART_PARITY_ODD:
- ulcon |= ULCON_PARITY_ODD;
- break;
- case UART_PARITY_EVEN:
- ulcon |= ULCON_PARITY_EVEN;
- break;
- case UART_PARITY_MARK:
- case UART_PARITY_SPACE:
- default:
- return (EINVAL);
- }
-
- if (stopbits == 2)
- ulcon |= ULCON_STOP;
-
- uart_setreg(bas, SSCOM_ULCON, ulcon);
-
- brd = sscomspeed(baudrate, bas->rclk);
- uart_setreg(bas, SSCOM_UBRDIV, brd);
-
- return (0);
-}
-
-struct uart_ops uart_s3c2410_ops = {
- .probe = s3c2410_probe,
- .init = s3c2410_init,
- .term = s3c2410_term,
- .putc = s3c2410_putc,
- .rxready = s3c2410_rxready,
- .getc = s3c2410_getc,
-};
-
-static int
-s3c2410_probe(struct uart_bas *bas)
-{
- return (0);
-}
-
-static void
-s3c2410_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
- int parity)
-{
- if (bas->rclk == 0)
- bas->rclk = s3c2410_pclk;
- KASSERT(bas->rclk != 0, ("s3c2410_init: Invalid rclk"));
-
- uart_setreg(bas, SSCOM_UCON, 0);
- uart_setreg(bas, SSCOM_UFCON,
- UFCON_TXTRIGGER_8 | UFCON_RXTRIGGER_8 |
- UFCON_TXFIFO_RESET | UFCON_RXFIFO_RESET |
- UFCON_FIFO_ENABLE);
- s3c24x0_uart_param(bas, baudrate, databits, stopbits, parity);
-
- /* Enable UART. */
- uart_setreg(bas, SSCOM_UCON, UCON_TXMODE_INT | UCON_RXMODE_INT |
- UCON_TOINT);
- uart_setreg(bas, SSCOM_UMCON, UMCON_RTS);
-}
-
-static void
-s3c2410_term(struct uart_bas *bas)
-{
- /* XXX */
-}
-
-static void
-s3c2410_putc(struct uart_bas *bas, int c)
-{
- while ((bus_space_read_4(bas->bst, bas->bsh, SSCOM_UFSTAT) &
- UFSTAT_TXFULL) == UFSTAT_TXFULL)
- continue;
-
- uart_setreg(bas, SSCOM_UTXH, c);
-}
-
-static int
-s3c2410_rxready(struct uart_bas *bas)
-{
- return ((uart_getreg(bas, SSCOM_UTRSTAT) & UTRSTAT_RXREADY) ==
- UTRSTAT_RXREADY);
-}
-
-static int
-s3c2410_getc(struct uart_bas *bas, struct mtx *mtx)
-{
- while (!sscom_rxrdy(bas->bst, bas->bsh))
- continue;
-
- return sscom_getc(bas->bst, bas->bsh);
-}
-static int s3c2410_bus_probe(struct uart_softc *sc);
-static int s3c2410_bus_attach(struct uart_softc *sc);
-static int s3c2410_bus_flush(struct uart_softc *, int);
-static int s3c2410_bus_getsig(struct uart_softc *);
-static int s3c2410_bus_ioctl(struct uart_softc *, int, intptr_t);
-static int s3c2410_bus_ipend(struct uart_softc *);
-static int s3c2410_bus_param(struct uart_softc *, int, int, int, int);
-static int s3c2410_bus_receive(struct uart_softc *);
-static int s3c2410_bus_setsig(struct uart_softc *, int);
-static int s3c2410_bus_transmit(struct uart_softc *);
-static void s3c2410_bus_grab(struct uart_softc *);
-static void s3c2410_bus_ungrab(struct uart_softc *);
-
-static kobj_method_t s3c2410_methods[] = {
- KOBJMETHOD(uart_probe, s3c2410_bus_probe),
- KOBJMETHOD(uart_attach, s3c2410_bus_attach),
- KOBJMETHOD(uart_flush, s3c2410_bus_flush),
- KOBJMETHOD(uart_getsig, s3c2410_bus_getsig),
- KOBJMETHOD(uart_ioctl, s3c2410_bus_ioctl),
- KOBJMETHOD(uart_ipend, s3c2410_bus_ipend),
- KOBJMETHOD(uart_param, s3c2410_bus_param),
- KOBJMETHOD(uart_receive, s3c2410_bus_receive),
- KOBJMETHOD(uart_setsig, s3c2410_bus_setsig),
- KOBJMETHOD(uart_transmit, s3c2410_bus_transmit),
- KOBJMETHOD(uart_grab, s3c2410_bus_grab),
- KOBJMETHOD(uart_ungrab, s3c2410_bus_ungrab),
-
- {0, 0 }
-};
-
-int
-s3c2410_bus_probe(struct uart_softc *sc)
-{
- switch(s3c2xx0_softc->sc_cpu) {
- case CPU_S3C2410:
- sc->sc_txfifosz = 16;
- sc->sc_rxfifosz = 16;
- break;
- case CPU_S3C2440:
- sc->sc_txfifosz = 64;
- sc->sc_rxfifosz = 64;
- break;
- default:
- return (ENXIO);
- }
-
- return (0);
-}
-
-static int
-s3c2410_bus_attach(struct uart_softc *sc)
-{
- uintptr_t irq;
-
- sc->sc_hwiflow = 0;
- sc->sc_hwoflow = 0;
-
- irq = rman_get_start(sc->sc_ires);
- arm_unmask_irq(irq);
- arm_unmask_irq(get_sub_irq(irq, RX_OFF));
- arm_unmask_irq(get_sub_irq(irq, TX_OFF));
- arm_unmask_irq(get_sub_irq(irq, ERR_OFF));
-
- return (0);
-}
-
-static int
-s3c2410_bus_transmit(struct uart_softc *sc)
-{
- uintptr_t irq;
-
- uart_lock(sc->sc_hwmtx);
-
- for (int i = 0; i < sc->sc_txdatasz; i++) {
- s3c2410_putc(&sc->sc_bas, sc->sc_txbuf[i]);
- uart_barrier(&sc->sc_bas);
- }
-
- sc->sc_txbusy = 1;
-
- uart_unlock(sc->sc_hwmtx);
-
- irq = rman_get_start(sc->sc_ires);
- arm_unmask_irq(get_sub_irq(irq, TX_OFF));
-
- return (0);
-}
-
-static int
-s3c2410_bus_setsig(struct uart_softc *sc, int sig)
-{
- return (0);
-}
-
-static int
-s3c2410_bus_receive(struct uart_softc *sc)
-{
-
- uart_rx_put(sc, uart_getreg(&sc->sc_bas, SSCOM_URXH));
- return (0);
-}
-
-static int
-s3c2410_bus_param(struct uart_softc *sc, int baudrate, int databits,
- int stopbits, int parity)
-{
- int error;
-
- if (sc->sc_bas.rclk == 0)
- sc->sc_bas.rclk = s3c2410_pclk;
- KASSERT(sc->sc_bas.rclk != 0, ("s3c2410_init: Invalid rclk"));
-
- uart_lock(sc->sc_hwmtx);
- error = s3c24x0_uart_param(&sc->sc_bas, baudrate, databits, stopbits,
- parity);
- uart_unlock(sc->sc_hwmtx);
-
- return (error);
-}
-
-static int
-s3c2410_bus_ipend(struct uart_softc *sc)
-{
- uint32_t ufstat, txmask, rxmask;
- uintptr_t irq;
- int ipend = 0;
-
- uart_lock(sc->sc_hwmtx);
- ufstat = bus_space_read_4(sc->sc_bas.bst, sc->sc_bas.bsh, SSCOM_UFSTAT);
- uart_unlock(sc->sc_hwmtx);
-
- txmask = rxmask = 0;
- switch (s3c2xx0_softc->sc_cpu) {
- case CPU_S3C2410:
- txmask = UFSTAT_TXCOUNT;
- rxmask = UFSTAT_RXCOUNT;
- break;
- case CPU_S3C2440:
- txmask = S3C2440_UFSTAT_TXCOUNT;
- rxmask = S3C2440_UFSTAT_RXCOUNT;
- break;
- }
- if ((ufstat & txmask) == 0) {
- if (sc->sc_txbusy != 0)
- ipend |= SER_INT_TXIDLE;
- irq = rman_get_start(sc->sc_ires);
- arm_mask_irq(get_sub_irq(irq, TX_OFF));
- }
- if ((ufstat & rxmask) > 0) {
- ipend |= SER_INT_RXREADY;
- }
-
- return (ipend);
-}
-
-static int
-s3c2410_bus_flush(struct uart_softc *sc, int what)
-{
- return (0);
-}
-
-static int
-s3c2410_bus_getsig(struct uart_softc *sc)
-{
- return (0);
-}
-
-static int
-s3c2410_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
-{
- return (EINVAL);
-}
-
-
-static void
-s3c2410_bus_grab(struct uart_softc *sc)
-{
- uintptr_t irq;
-
- irq = rman_get_start(sc->sc_ires);
- arm_mask_irq(get_sub_irq(irq, RX_OFF));
-}
-
-static void
-s3c2410_bus_ungrab(struct uart_softc *sc)
-{
- uintptr_t irq;
-
- irq = rman_get_start(sc->sc_ires);
- arm_unmask_irq(get_sub_irq(irq, RX_OFF));
-}
-
-struct uart_class uart_s3c2410_class = {
- "s3c2410 class",
- s3c2410_methods,
- 1,
- .uc_ops = &uart_s3c2410_ops,
- .uc_range = 8,
- .uc_rclk = 0,
- .uc_rshift = 0
-};
+++ /dev/null
-/* $NetBSD: sscom_var.h,v 1.5 2003/08/04 12:28:49 bsh Exp $ */
-
-/*-
- * Copyright (c) 2002, 2003 Fujitsu Component Limited
- * Copyright (c) 2002, 2003 Genetec Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of The Fujitsu Component Limited nor the name of
- * Genetec corporation may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC
- * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
- * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC
- * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-/* derived from sys/dev/ic/comvar.h */
-
-/*-
- * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * This product includes software developed by Christopher G. Demetriou
- * for the NetBSD Project.
- * 4. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-#ifndef _ARM_S3C2XX0_SSCOM_VAR_H
-#define _ARM_S3C2XX0_SSCOM_VAR_H
-
-
-/* Hardware flag masks */
-#define SSCOM_HW_FLOW 0x02
-#define SSCOM_HW_DEV_OK 0x04
-#define SSCOM_HW_CONSOLE 0x08
-#define SSCOM_HW_KGDB 0x10
-#define SSCOM_HW_TXINT 0x20
-#define SSCOM_HW_RXINT 0x40
-
-/* Buffer size for character buffer */
-#define SSCOM_RING_SIZE 2048
-
-#define sscom_rxrdy(iot,ioh) \
- (bus_space_read_1((iot), (ioh), SSCOM_UTRSTAT) & UTRSTAT_RXREADY)
-#define sscom_getc(iot,ioh) bus_space_read_1((iot), (ioh), SSCOM_URXH)
-#define sscom_geterr(iot,ioh) bus_space_read_1((iot), (ioh), SSCOM_UERSTAT)
-
-#endif /* _ARM_S3C2XX0_SSCOM_VAR_H */
projects / people / julieng / freebsd.git / commitdiff