x86/intel: Fix PERF_GLOBAL fixup when virtualised

Logic using performance counters needs to look at
MSR_MISC_ENABLE.PERF_AVAILABLE before touching any other resources.

When virtualised under ESX, Xen dies with a #GP fault trying to read
MSR_CORE_PERF_GLOBAL_CTRL.

Factor this logic out into a separate function (it's already too squashed to
the RHS), and insert a check of MSR_MISC_ENABLE.PERF_AVAILABLE.

This also avoids setting X86_FEATURE_ARCH_PERFMON if MSR_MISC_ENABLE says that
PERF is unavailable, although oprofile (the only consumer of this flag)
cross-checks too.

Fixes: 6bdb965178bb ("x86/intel: ensure Global Performance Counter Control is setup correctly")
Reported-by: Jonathan Katz <jonathan.katz@aptar.com>
Link: https://xcp-ng.org/forum/topic/10286/nesting-xcp-ng-on-esx-8
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
Tested-by: Jonathan Katz <jonathan.katz@aptar.com>
master commit: dd05d265b8abda4cc7206b29cd71b77fb46658bf
master date: 2025-01-28 11:19:45 +0000

diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c
index af56e57bd8ab798bafb051b15f4a5ecbd1ad0ac7..bb9c6220de80228dc1266114f2ca97b06e7eb823 100644 (file)
--- a/xen/arch/x86/cpu/intel.c
+++ b/xen/arch/x86/cpu/intel.c
@@ -535,39 +535,49 @@ static void intel_log_freq(const struct cpuinfo_x86 *c)
     printk("%u MHz\n", (factor * max_ratio + 50) / 100);
 }
 
+static void init_intel_perf(struct cpuinfo_x86 *c)
+{
+    uint64_t val;
+    unsigned int eax, ver, nr_cnt;
+
+    if ( c->cpuid_level <= 9 ||
+         ({  rdmsrl(MSR_IA32_MISC_ENABLE, val);
+             !(val & MSR_IA32_MISC_ENABLE_PERF_AVAIL); }) )
+        return;
+
+    eax = cpuid_eax(10);
+    ver = eax & 0xff;
+    nr_cnt = (eax >> 8) & 0xff;
+
+    if ( ver && nr_cnt > 1 && nr_cnt <= 32 )
+    {
+        unsigned int cnt_mask = (1UL << nr_cnt) - 1;
+
+        /*
+         * On (some?) Sapphire/Emerald Rapids platforms each package-BSP
+         * starts with all the enable bits for the general-purpose PMCs
+         * cleared.  Adjust so counters can be enabled from EVNTSEL.
+         */
+        rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, val);
+
+        if ( (val & cnt_mask) != cnt_mask )
+        {
+            printk("FIRMWARE BUG: CPU%u invalid PERF_GLOBAL_CTRL: %#"PRIx64" adjusting to %#"PRIx64"\n",
+                   smp_processor_id(), val, val | cnt_mask);
+            wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, val | cnt_mask);
+        }
+
+        __set_bit(X86_FEATURE_ARCH_PERFMON, c->x86_capability);
+    }
+}
+
 static void cf_check init_intel(struct cpuinfo_x86 *c)
 {
        /* Detect the extended topology information if available */
        detect_extended_topology(c);
 
        init_intel_cacheinfo(c);
-       if (c->cpuid_level > 9) {
-               unsigned eax = cpuid_eax(10);
-               unsigned int cnt = (eax >> 8) & 0xff;
-
-               /* Check for version and the number of counters */
-               if ((eax & 0xff) && (cnt > 1) && (cnt <= 32)) {
-                       uint64_t global_ctrl;
-                       unsigned int cnt_mask = (1UL << cnt) - 1;
-
-                       /*
-                        * On (some?) Sapphire/Emerald Rapids platforms each
-                        * package-BSP starts with all the enable bits for the
-                        * general-purpose PMCs cleared.  Adjust so counters
-                        * can be enabled from EVNTSEL.
-                        */
-                       rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, global_ctrl);
-                       if ((global_ctrl & cnt_mask) != cnt_mask) {
-                               printk("CPU%u: invalid PERF_GLOBAL_CTRL: %#"
-                                      PRIx64 " adjusting to %#" PRIx64 "\n",
-                                      smp_processor_id(), global_ctrl,
-                                      global_ctrl | cnt_mask);
-                               wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
-                                      global_ctrl | cnt_mask);
-                       }
-                       __set_bit(X86_FEATURE_ARCH_PERFMON, c->x86_capability);
-               }
-       }
+       init_intel_perf(c);
 
        if ( !cpu_has(c, X86_FEATURE_XTOPOLOGY) )
        {