]> xenbits.xensource.com Git - ovmf.git/commitdiff
MdePkg/BaseLib AARCH64: Make asm files BTI compatible
authorArd Biesheuvel <ardb@kernel.org>
Sat, 25 Mar 2023 16:37:10 +0000 (17:37 +0100)
committermergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Thu, 30 Mar 2023 11:05:22 +0000 (11:05 +0000)
Add the BTI instructions and the associated note to make the AArch64 asm
objects compatible with BTI enforcement.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.S
MdePkg/Library/BaseLib/AArch64/DisableInterrupts.S
MdePkg/Library/BaseLib/AArch64/EnableInterrupts.S
MdePkg/Library/BaseLib/AArch64/GetInterruptsState.S
MdePkg/Library/BaseLib/AArch64/MemoryFence.S
MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.S
MdePkg/Library/BaseLib/AArch64/SpeculationBarrier.S
MdePkg/Library/BaseLib/AArch64/SwitchStack.S

index 7524fb18820c2fa3fb3328cefd192cdb1e98ab50..24a1ac371884bb1da5f52b7aa3c5d396c9d49b09 100644 (file)
@@ -27,5 +27,6 @@ GCC_ASM_EXPORT(CpuBreakpoint)
 #  );\r
 #\r
 ASM_PFX(CpuBreakpoint):\r
+    AARCH64_BTI(c)\r
     svc   0xdbdb    // Superviser exception. Takes 16bit arg -> Armv7 had 'swi' here.\r
     ret\r
index f0faf16b06a3fcae70a8ca0172488a4f6972594b..3f562461614ad2940bc9d6eec5766e4664edee38 100644 (file)
@@ -26,5 +26,6 @@ GCC_ASM_EXPORT(DisableInterrupts)
 #  );\r
 #\r
 ASM_PFX(DisableInterrupts):\r
+   AARCH64_BTI(c)\r
    msr  daifset, #DAIF_WR_IRQ_BIT\r
    ret\r
index 97eeb13fbe5d2145a44b6a7f332109990bfa5845..0f1377f51c7e88f7ebc0881a17c7be85b5848aeb 100644 (file)
@@ -26,5 +26,6 @@ GCC_ASM_EXPORT(EnableInterrupts)
 #  );\r
 #\r
 ASM_PFX(EnableInterrupts):\r
+    AARCH64_BTI(c)\r
     msr  daifclr, #DAIF_WR_IRQ_BIT\r
     ret\r
index bf8b829bb2b1749d839b2ad3c7f84f53ad33c783..26787a5b9bddcd7ec8c3b5866046cc4f4d23a4b2 100644 (file)
@@ -33,6 +33,7 @@ GCC_ASM_EXPORT(GetInterruptState)
 # );\r
 #\r
 ASM_PFX(GetInterruptState):\r
+    AARCH64_BTI(c)\r
     mrs    x0, daif\r
     tst    x0, #DAIF_RD_IRQ_BIT   // Check IRQ mask; set Z=1 if clear/unmasked\r
     cset   w0, eq                 // if Z=1 (eq) return 1, else 0\r
index e553bd2dc9fcf63f60ab3f929a5e00f8980476a4..ad5b92a9a72bd65c2ca1c5b64a0739b11a8e7490 100644 (file)
@@ -28,6 +28,7 @@ GCC_ASM_EXPORT(MemoryFence)
 #  );\r
 #\r
 ASM_PFX(MemoryFence):\r
+    AARCH64_BTI(c)\r
     // System wide Data Memory Barrier.\r
     dmb sy\r
     ret\r
index 1d5cfbf64470452fabb590e495b8889b9fd525a1..0d902d94d31c4a3565b83ef11e59477c62c5fbce 100644 (file)
@@ -46,6 +46,7 @@ GCC_ASM_EXPORT(InternalLongJump)
 #  );\r
 #\r
 ASM_PFX(SetJump):\r
+        AARCH64_BTI(c)\r
         mov     x16, sp // use IP0 so save SP\r
 #define REG_PAIR(REG1, REG2, OFFS)      stp REG1, REG2, [x0, OFFS]\r
 #define REG_ONE(REG1, OFFS)             str REG1, [x0, OFFS]\r
@@ -75,6 +76,7 @@ ASM_PFX(SetJump):
 #  );\r
 #\r
 ASM_PFX(InternalLongJump):\r
+        AARCH64_BTI(c)\r
 #define REG_PAIR(REG1, REG2, OFFS)      ldp REG1, REG2, [x0, OFFS]\r
 #define REG_ONE(REG1, OFFS)             ldr REG1, [x0, OFFS]\r
         GPR_LAYOUT\r
index a20d6aed0cdd52842e6a39cc529c674d1262c6b5..248ee01e52c2736781ba65925439269f67bee6b8 100644 (file)
@@ -28,6 +28,7 @@ GCC_ASM_EXPORT(SpeculationBarrier)
 #  );\r
 #\r
 ASM_PFX(SpeculationBarrier):\r
+    AARCH64_BTI(c)\r
     dsb  sy\r
     isb\r
     ret\r
index f3bce6a09bc2d555a02bdd0e5efd2bf72704049d..837c65b45e73024e8fc16ed57b165a6dd7860df6 100644 (file)
@@ -35,6 +35,7 @@ GCC_ASM_EXPORT(CpuPause)
 #  );\r
 #\r
 ASM_PFX(InternalSwitchStackAsm):\r
+    AARCH64_BTI(c)\r
     mov   x29, #0\r
     mov   x30, x0\r
     mov   sp, x3\r
@@ -57,6 +58,7 @@ ASM_PFX(InternalSwitchStackAsm):
 #  )\r
 #\r
 ASM_PFX(CpuPause):\r
+    AARCH64_BTI(c)\r
     nop\r
     nop\r
     nop\r