}
return (ln2size);
}
-
+
/* return log2 of address range supported by map register */
static int
free(used, M_DEVBUF);
return (EINVAL);
}
-
+
/* Make sure none of the resources are allocated. */
for (i = 0; i < msix->msix_table_len; i++) {
if (msix->msix_table[i].mte_vector == 0)
struct msix_table_entry *mte;
struct msix_vector *mv;
uint64_t addr;
- uint32_t data;
+ uint32_t data;
int error, i, j;
/*
if (error)
return (error);
- /* Disable decoding for device ROMs. */
+ /* Disable decoding for device ROMs. */
if (device_get_parent(child) == dev) {
dinfo = device_get_ivars(child);
if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid))
static int pcib_power_for_sleep(device_t pcib, device_t dev,
int *pstate);
static uint16_t pcib_ari_get_rid(device_t pcib, device_t dev);
-static uint32_t pcib_read_config(device_t dev, u_int b, u_int s,
+static uint32_t pcib_read_config(device_t dev, u_int b, u_int s,
u_int f, u_int reg, int width);
static void pcib_write_config(device_t dev, u_int b, u_int s,
u_int f, u_int reg, uint32_t val, int width);
free(w->res, M_DEVBUF);
w->res = newarray;
w->count += count;
-
+
for (i = 0; i < count; i++) {
error = rman_manage_region(&w->rman, rman_get_start(res[i]),
rman_get_end(res[i]));
sc->pmembase = PCI_PPBMEMBASE(0, pmemlow);
pmemlow = pci_read_config(dev, PCIR_PMLIMITL_1, 2);
- if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64)
+ if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64)
sc->pmemlimit = PCI_PPBMEMLIMIT(
pci_read_config(dev, PCIR_PMLIMITH_1, 4), pmemlow);
else
pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
{
struct pcib_softc *sc = device_get_softc(dev);
-
+
switch (which) {
case PCIB_IVAR_DOMAIN:
*result = sc->domain;
return (0);
}
}
- return (ENOSPC);
+ return (ENOSPC);
}
-
+
wmask = (1ul << w->step) - 1;
if (RF_ALIGNMENT(flags) < w->step) {
flags &= ~RF_ALIGNMENT_MASK;
KASSERT(w->base == rman_get_start(res),
("existing resource mismatch"));
force_64k_base = 0;
- }
+ }
error = bus_adjust_resource(sc->dev, type, res, force_64k_base ?
rman_get_start(res) : base, limit);
* is set up to, or capable of handling them.
*/
struct resource *
-pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
+pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
u_long start, u_long end, u_long count, u_int flags)
{
struct pcib_softc *sc = device_get_softc(dev);
int parent_intpin;
int intnum;
- /*
+ /*
*
* The PCI standard defines a swizzle of the child-side device/intpin to
* the parent-side intpin as follows.
return (0);
}
-