#define MSR_PERF_GLOBAL_STATUS 0x0000038e
#define MSR_PERF_GLOBAL_CTRL 0x0000038f
#define MSR_PERF_GLOBAL_OVF_CTRL 0x00000390
+
+#define MSR_VMX_BASIC 0x00000480
+
#define MSR_A_PMC(n) (0x000004c1 + (n))
#define MSR_X2APIC_REGS 0x00000800
};
} msr_feature_control_t;
+typedef union msr_vmx_basic {
+ uint64_t raw;
+ struct {
+ uint32_t vmcs_rev_id:31;
+ bool mbz:1;
+ uint32_t vmcs_size:13;
+ uint32_t :3;
+ bool paddr_32bit:1;
+ bool smm_dual:1;
+ uint32_t vmcs_mem_type:4;
+ bool inouts_exit_info:1;
+ bool true_ctls:1;
+ };
+} msr_vmx_basic_t;
+
#endif /* !__ASSEMBLY__ */
#endif /* XFT_X86_MSR_INDEX_H */
xtf_failure("Fail: Successfully wrote to MSR_FEATURE_CONTROL\n");
}
+static void test_msr_vmx_basic(void)
+{
+ msr_vmx_basic_t basic;
+
+ if ( rdmsr_safe(MSR_VMX_BASIC, &basic.raw) )
+ return xtf_failure("Fail: Fault when reading MSR_VMX_BASIC\n");
+
+ if ( basic.mbz )
+ xtf_failure("Fail: MSR_VMX_BASIC[31] is not 0\n");
+
+ if ( basic.vmcs_size == 0 )
+ xtf_failure("Fail: VMCS size reported as 0\n");
+ else if ( basic.vmcs_size > 4096 )
+ xtf_failure("Fail: VMCS size (%u) exceeds 4096 limit\n",
+ basic.vmcs_size);
+
+ if ( cpu_has_lm && basic.paddr_32bit )
+ xtf_failure("Fail: Physical address width limited to 32 bits\n");
+
+ if ( !wrmsr_safe(MSR_VMX_BASIC, basic.raw) )
+ xtf_failure("Fail: Successfully wrote to MSR_VMX_BASIC\n");
+}
+
void test_msr_vmx(void)
{
printk("Test: MSRs\n");
test_msr_feature_control();
+ test_msr_vmx_basic();
}
/*