[IA64] translate_domain_pte must handle ED bit and ignre bit[63:53]

made translate_domain_pte() aware _PAGE_ED bits.
_PAGE_PPN_MASK doesn't mask ED bit.
ED bit must be handled explicitly.
This case can occur by vcpu_itc_d().

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>

diff --git a/xen/arch/ia64/xen/process.c b/xen/arch/ia64/xen/process.c
index a82925348b7ea7f0b0df9c5a2d5e8a3d4c15cef1..887fa3d86a7d73e65eee61805f59e284692bd8c2 100644 (file)
--- a/xen/arch/ia64/xen/process.c
+++ b/xen/arch/ia64/xen/process.c
@@ -87,9 +87,12 @@ unsigned long translate_domain_pte(unsigned long pteval,
        struct domain *d = current->domain;
        unsigned long mask, pteval2, mpaddr;
 
+       pteval &= ((1UL << 53) - 1);// ignore [63:53] bits
+
        // FIXME address had better be pre-validated on insert
        mask = ~itir_mask(itir);
-       mpaddr = ((pteval & _PAGE_PPN_MASK) & ~mask) | (address & mask);
+       mpaddr = (((pteval & ~_PAGE_ED) & _PAGE_PPN_MASK) & ~mask) |
+                (address & mask);
        if (d == dom0) {
                if (mpaddr < dom0_start || mpaddr >= dom0_start + dom0_size) {
                        /*
@@ -114,6 +117,7 @@ unsigned long translate_domain_pte(unsigned long pteval,
        }
        pteval2 = lookup_domain_mpa(d,mpaddr);
        pteval2 &= _PAGE_PPN_MASK; // ignore non-addr bits
+       pteval2 |= (pteval & _PAGE_ED);
        pteval2 |= _PAGE_PL_2; // force PL0->2 (PL3 is unaffected)
        pteval2 = (pteval & ~_PAGE_PPN_MASK) | pteval2;
        return pteval2;