mov %ss, REF(saved_ss)
- sgdt REF(saved_gdt)
- sidt REF(saved_idt)
- sldt REF(saved_ldt)
-
mov %cr0, GREG(ax)
mov GREG(ax), REF(saved_cr0)
ENTRY(__ret_point)
+ lgdt boot_gdtr(%rip)
/* mmu_cr4_features contains latest cr4 setting */
mov REF(mmu_cr4_features), GREG(ax)
mov REF(saved_cr0), GREG(ax)
mov GREG(ax), %cr0
- lgdt REF(saved_gdt)
- lidt REF(saved_idt)
- lldt REF(saved_ldt)
-
mov REF(saved_ss), %ss
LOAD_GREG(sp)
DECLARE_GREG(14)
DECLARE_GREG(15)
-saved_gdt: .quad 0,0
-saved_idt: .quad 0,0
-saved_ldt: .quad 0,0
-
saved_cr0: .quad 0
saved_cr3: .quad 0
__set_intr_gate(n, 0, addr);
}
-void load_TR(void)
-{
- struct tss64 *tss = &this_cpu(tss_page).tss;
- struct desc_ptr old_gdt, tss_gdt = {
- .base = (long)(this_cpu(gdt) - FIRST_RESERVED_GDT_ENTRY),
- .limit = LAST_RESERVED_GDT_BYTE
- };
-
- _set_tssldt_desc(
- this_cpu(gdt) + TSS_ENTRY - FIRST_RESERVED_GDT_ENTRY,
- (unsigned long)tss, sizeof(*tss) - 1, SYS_DESC_tss_avail);
- _set_tssldt_desc(
- this_cpu(compat_gdt) + TSS_ENTRY - FIRST_RESERVED_GDT_ENTRY,
- (unsigned long)tss, sizeof(*tss) - 1, SYS_DESC_tss_busy);
-
- /* Switch to non-compat GDT (which has B bit clear) to execute LTR. */
- asm volatile (
- "sgdt %0; lgdt %2; ltr %w1; lgdt %0"
- : "=m" (old_gdt) : "rm" (TSS_SELECTOR), "m" (tss_gdt) : "memory" );
-}
-
static unsigned int calc_ler_msr(void)
{
switch ( boot_cpu_data.x86_vendor )
DECLARE_PER_CPU(l1_pgentry_t, compat_gdt_l1e);
DECLARE_PER_CPU(bool, full_gdt_loaded);
-extern void load_TR(void);
-
static inline void lgdt(const struct desc_ptr *gdtr)
{
__asm__ __volatile__ ( "lgdt %0" :: "m" (*gdtr) : "memory" );