amd/iommu: fix present bit checking when clearing PTE

The current check for the present bit is wrong, since the present bit
is located in the low part of the entry.

Fixes: e8afe1124cc1 ("iommu: elide flushing for higher order map/unmap operations")
Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
Reviewed-by: Paul Durrant <paul.durrant@citrix.com>
Reviewed-by: Brian Woods <brian.woods@amd.com>
Release-acked-by: Juergen Gross <jgross@suse.com>

diff --git a/xen/drivers/passthrough/amd/iommu_map.c b/xen/drivers/passthrough/amd/iommu_map.c
index 99ac0a68625ced2efd48a34e16bfc6938d0b7a80..67329b0c95dc8cf941fe051e9520ac64eb80b0ab 100644 (file)
--- a/xen/drivers/passthrough/amd/iommu_map.c
+++ b/xen/drivers/passthrough/amd/iommu_map.c
@@ -39,15 +39,13 @@ static unsigned int clear_iommu_pte_present(unsigned long l1_mfn,
                                             unsigned long dfn)
 {
     uint64_t *table, *pte;
-    uint32_t entry;
     unsigned int flush_flags;
 
     table = map_domain_page(_mfn(l1_mfn));
 
     pte = (table + pfn_to_pde_idx(dfn, 1));
-    entry = *pte >> 32;
 
-    flush_flags = get_field_from_reg_u32(entry, IOMMU_PTE_PRESENT_MASK,
+    flush_flags = get_field_from_reg_u32(*pte, IOMMU_PTE_PRESENT_MASK,
                                          IOMMU_PTE_PRESENT_SHIFT) ?
                                          IOMMU_FLUSHF_modified : 0;