pl4e = l4start + l4_table_offset(vphysmap_start);
if ( !l4e_get_intpte(*pl4e) )
{
- page = alloc_domheap_page(d, 0);
+ page = alloc_domheap_page(d, MEMF_no_scrub);
if ( !page )
break;
vphysmap_end >= vphysmap_start + (1UL << L3_PAGETABLE_SHIFT) &&
(page = alloc_domheap_pages(d,
L3_PAGETABLE_SHIFT - PAGE_SHIFT,
- 0)) != NULL )
+ MEMF_no_scrub)) != NULL )
{
*pl3e = l3e_from_page(page, L1_PROT|_PAGE_DIRTY|_PAGE_PSE);
vphysmap_start += 1UL << L3_PAGETABLE_SHIFT;
continue;
}
- if ( (page = alloc_domheap_page(d, 0)) == NULL )
+ if ( (page = alloc_domheap_page(d, MEMF_no_scrub)) == NULL )
break;
/* No mapping, PGC_allocated + page-table page. */
vphysmap_end >= vphysmap_start + (1UL << L2_PAGETABLE_SHIFT) &&
(page = alloc_domheap_pages(d,
L2_PAGETABLE_SHIFT - PAGE_SHIFT,
- 0)) != NULL )
+ MEMF_no_scrub)) != NULL )
{
*pl2e = l2e_from_page(page, L1_PROT|_PAGE_DIRTY|_PAGE_PSE);
vphysmap_start += 1UL << L2_PAGETABLE_SHIFT;
continue;
}
- if ( (page = alloc_domheap_page(d, 0)) == NULL )
+ if ( (page = alloc_domheap_page(d, MEMF_no_scrub)) == NULL )
break;
/* No mapping, PGC_allocated + page-table page. */
pl1e += l1_table_offset(vphysmap_start);
BUG_ON(l1e_get_intpte(*pl1e));
- page = alloc_domheap_page(d, 0);
+ page = alloc_domheap_page(d, MEMF_no_scrub);
if ( !page )
break;
order = last_order;
else if ( max_pages & (max_pages - 1) )
--order;
- while ( (page = alloc_domheap_pages(d, order, dom0_memflags)) == NULL )
+ while ( (page = alloc_domheap_pages(d, order, dom0_memflags |
+ MEMF_no_scrub)) == NULL )
if ( order-- == 0 )
break;
if ( page )
if ( d->tot_pages + (1 << order) > d->max_pages )
continue;
- pg2 = alloc_domheap_pages(d, order, MEMF_exact_node);
+ pg2 = alloc_domheap_pages(d, order, MEMF_exact_node | MEMF_no_scrub);
if ( pg2 > page )
{
free_domheap_pages(page, free_order);
vphysmap_start = parms.p2m_base;
vphysmap_end = vphysmap_start + nr_pages * sizeof(unsigned long);
}
- page = alloc_domheap_pages(d, order, 0);
+ page = alloc_domheap_pages(d, order, MEMF_no_scrub);
if ( page == NULL )
panic("Not enough RAM for domain 0 allocation\n");
alloc_spfn = mfn_x(page_to_mfn(page));
((mfn + count - 1) >> (d->arch.physaddr_bitsize - PAGE_SHIFT)) )
{
order = get_order_from_pages(count);
- page = alloc_domheap_pages(d, order, 0);
+ page = alloc_domheap_pages(d, order, MEMF_no_scrub);
if ( !page )
panic("Not enough RAM for domain 0 initrd\n");
for ( count = -count; order--; )
}
else
{
- page = alloc_domheap_page(d, MEMF_no_owner);
+ page = alloc_domheap_page(d, MEMF_no_owner | MEMF_no_scrub);
if ( !page )
panic("Not enough RAM for domain 0 PML4\n");
page->u.inuse.type_info = PGT_l4_page_table|PGT_validated|1;