#include <xen/8250-uart.h>
-/* 8250 UART wait UART to be ready to transmit
+/*
+ * 8250 UART wait UART to be ready to transmit
* rb: register which contains the UART base address
- * rc: scratch register */
+ * rc: scratch register
+ */
.macro early_uart_ready rb rc
1:
ldr \rc, [\rb, #(UART_LSR << EARLY_UART_REG_SHIFT)] /* Read LSR */
beq 1b /* Wait for the UART to be ready */
.endm
-/* 8250 UART transmit character
+/*
+ * 8250 UART transmit character
* rb: register which contains the UART base address
- * rt: register which contains the character to transmit */
+ * rt: register which contains the character to transmit
+ */
.macro early_uart_transmit rb rt
str \rt, [\rb, #UART_THR] /* Write Transmit buffer */
.endm
#include <asm/exynos4210-uart.h>
-/* Exynos 5 UART wait UART to be ready to transmit
+/*
+ * Exynos 5 UART wait UART to be ready to transmit
* rb: register which contains the UART base address
- * rc: scratch register */
+ * rc: scratch register
+ */
.macro early_uart_ready rb rc
1:
ldr \rc, [\rb, #UTRSTAT] /* <- UTRSTAT (Flag register) */
beq 1b /* Wait for the UART to be ready */
.endm
-/* Exynos 5 UART transmit character
+/*
+ * Exynos 5 UART transmit character
* rb: register which contains the UART base address
- * rt: register which contains the character to transmit */
+ * rt: register which contains the character to transmit
+ */
.macro early_uart_transmit rb rt
str \rt, [\rb, #UTXH] /* -> UTXH (Data Register) */
.endm
#include <asm/pl011-uart.h>
-/* PL011 UART initialization
+/*
+ * PL011 UART initialization
* rb: register which contains the UART base address
* rc: scratch register 1
- * rd: scratch register 2 (unused here) */
+ * rd: scratch register 2 (unused here)
+ */
.macro early_uart_init rb, rc, rd
mov \rc, #(7372800 / EARLY_PRINTK_BAUD % 16)
str \rc, [\rb, #FBRD] /* -> UARTFBRD (Baud divisor fraction) */
str \rc, [\rb, #CR] /* -> UARTCR (Control Register) */
.endm
-/* PL011 UART wait UART to be ready to transmit
+/*
+ * PL011 UART wait UART to be ready to transmit
* rb: register which contains the UART base address
- * rc: scratch register */
+ * rc: scratch register
+ */
.macro early_uart_ready rb, rc
1:
ldr \rc, [\rb, #FR] /* <- UARTFR (Flag register) */
bne 1b /* Wait for the UART to be ready */
.endm
-/* PL011 UART transmit character
+/*
+ * PL011 UART transmit character
* rb: register which contains the UART base address
- * rt: register which contains the character to transmit */
+ * rt: register which contains the character to transmit
+ */
.macro early_uart_transmit rb, rt
str \rt, [\rb, #DR] /* -> UARTDR (Data Register) */
.endm
#include <asm/scif-uart.h>
-/* SCIF UART wait UART to be ready to transmit
+/*
+ * SCIF UART wait UART to be ready to transmit
* rb: register which contains the UART base address
* rc: scratch register
*/
beq 1b /* Wait for the UART to be ready */
.endm
-/* SCIF UART transmit character
+/*
+ * SCIF UART transmit character
* rb: register which contains the UART base address
* rt: register which contains the character to transmit
*/
#include EARLY_PRINTK_INC
#endif
-/* Print a character on the UART - this function is called by C
- * r0: character to print */
+/*
+ * Print a character on the UART - this function is called by C
+ * r0: character to print
+ */
GLOBAL(early_putch)
ldr r1, =EARLY_UART_VIRTUAL_ADDRESS /* r1 := VA UART base address */
early_uart_ready r1, r2
.arm
- /* This must be the very first address in the loaded image.
+ /*
+ * This must be the very first address in the loaded image.
* It should be linked at XEN_VIRT_START, and loaded at any
* 4K-aligned address. All of text+data+bss must fit in 2MB,
- * or the initial pagetable code below will need adjustment. */
+ * or the initial pagetable code below will need adjustment.
+ */
GLOBAL(start)
- /* zImage magic header, see:
+ /*
+ * zImage magic header, see:
* http://www.simtec.co.uk/products/SWLINUX/files/booting_article.html#d0e309
*/
.rept 8
mcr CP32(r0, HMAIR0)
mcr CP32(r1, HMAIR1)
- /* Set up the HTCR:
+ /*
+ * Set up the HTCR:
* PT walks use Inner-Shareable accesses,
* PT walks are write-back, write-allocate in both cache levels,
- * Full 32-bit address space goes through this table. */
+ * Full 32-bit address space goes through this table.
+ */
ldr r0, =(TCR_RES1|TCR_SH0_IS|TCR_ORGN0_WBWA|TCR_IRGN0_WBWA|TCR_T0SZ(0))
mcr CP32(r0, HTCR)
- /* Set up the HSCTLR:
+ /*
+ * Set up the HSCTLR:
* Exceptions in LE ARM,
* Low-latency IRQs disabled,
* Write-implies-XN disabled (for now),
* D-cache disabled (for now),
* I-cache enabled,
* Alignment checking enabled,
- * MMU translation disabled (for now). */
+ * MMU translation disabled (for now).
+ */
ldr r0, =(HSCTLR_BASE|SCTLR_A)
mcr CP32(r0, HSCTLR)
- /* Rebuild the boot pagetable's first-level entries. The structure
+ /*
+ * Rebuild the boot pagetable's first-level entries. The structure
* is described in mm.c.
*
* After the CPU enables paging it will add the fixmap mapping
* to these page tables, however this may clash with the 1:1
* mapping. So each CPU must rebuild the page tables here with
- * the 1:1 in place. */
+ * the 1:1 in place.
+ */
- /* If Xen is loaded at exactly XEN_VIRT_START then we don't
+ /*
+ * If Xen is loaded at exactly XEN_VIRT_START then we don't
* need an additional 1:1 mapping, the virtual mapping will
* suffice.
*/
cmp r1, #(LPAE_ENTRIES<<3) /* 512*8-byte entries per page */
blo 1b
- /* Defer fixmap and dtb mapping until after paging enabled, to
- * avoid them clashing with the 1:1 mapping. */
+ /*
+ * Defer fixmap and dtb mapping until after paging enabled, to
+ * avoid them clashing with the 1:1 mapping.
+ */
/* boot pagetable setup complete */
mov pc, r1 /* Get a proper vaddr into PC */
paging:
- /* Now we can install the fixmap and dtb mappings, since we
- * don't need the 1:1 map any more */
+ /*
+ * Now we can install the fixmap and dtb mappings, since we
+ * don't need the 1:1 map any more
+ */
dsb
#if defined(CONFIG_EARLY_PRINTK) /* Fixmap is only used by early printk */
- /* Non-boot CPUs don't need to rebuild the fixmap itself, just
- * the mapping from boot_second to xen_fixmap */
+ /*
+ * Non-boot CPUs don't need to rebuild the fixmap itself, just
+ * the mapping from boot_second to xen_fixmap
+ */
teq r12, #0
bne 1f
teq r12, #0
beq launch
- /* Non-boot CPUs need to move on to the proper pagetables, which were
- * setup in init_secondary_pagetables. */
+ /*
+ * Non-boot CPUs need to move on to the proper pagetables, which were
+ * setup in init_secondary_pagetables.
+ */
ldr r4, =init_ttbr /* VA of HTTBR value stashed by CPU 0 */
ldrd r4, r5, [r4] /* Actual value */
GLOBAL(_end_boot)
-/* Copy Xen to new location and switch TTBR
+/*
+ * Copy Xen to new location and switch TTBR
* r1:r0 ttbr
* r2 source address
* r3 destination address
* Source and destination must be word aligned, length is rounded up
* to a 16 byte boundary.
*
- * MUST BE VERY CAREFUL when saving things to RAM over the copy */
+ * MUST BE VERY CAREFUL when saving things to RAM over the copy
+ */
ENTRY(relocate_xen)
push {r4,r5,r6,r7,r8,r9,r10,r11}
mov pc, lr
#ifdef CONFIG_EARLY_PRINTK
-/* Bring up the UART.
+/*
+ * Bring up the UART.
* r11: Early UART base address
- * Clobbers r0-r2 */
+ * Clobbers r0-r2
+ */
init_uart:
#ifdef EARLY_PRINTK_INIT_UART
early_uart_init r11, r1, r2
1: .asciz "- UART enabled -\r\n"
.align 4
-/* Print early debug messages.
+/*
+ * Print early debug messages.
* r0: Nul-terminated string to print.
* r11: Early UART base address
- * Clobbers r0-r1 */
+ * Clobbers r0-r1
+ */
puts:
early_uart_ready r11, r1
ldrb r1, [r0], #1 /* Load next char */
early_uart_transmit r11, r1
b puts
-/* Print a 32-bit number in hex. Specific to the PL011 UART.
+/*
+ * Print a 32-bit number in hex. Specific to the PL011 UART.
* r0: Number to print.
* r11: Early UART base address
- * Clobbers r0-r3 */
+ * Clobbers r0-r3
+ */
putn:
adr r1, hex
mov r3, #8
mov r0, r1
ldmfd sp!, {r4, r10, pc}
-/* Read processor ID register (CP#15, CR0), and Look up in the linker-built
+/*
+ * Read processor ID register (CP#15, CR0), and Look up in the linker-built
* supported processor list. Note that we can't use the absolute addresses for
* the __proc_info lists since we aren't running with the MMU on (and therefore,
* we are not in correct address space). We have to calculate the offset.
#include <xen/8250-uart.h>
-/* UART wait UART to be ready to transmit
+/*
+ * UART wait UART to be ready to transmit
* xb: register which contains the UART base address
- * c: scratch register */
+ * c: scratch register
+ */
.macro early_uart_ready xb c
1:
ldrb w\c, [\xb, #UART_LSR << EARLY_UART_REG_SHIFT]
b.ne 1b
.endm
-/* UART transmit character
+/*
+ * UART transmit character
* xb: register which contains the UART base address
- * wt: register which contains the character to transmit */
+ * wt: register which contains the character to transmit
+ */
.macro early_uart_transmit xb wt
/* UART_THR transmit holding */
strb \wt, [\xb, #UART_THR << EARLY_UART_REG_SHIFT]
#include <asm/asm_defns.h>
#include <asm/cadence-uart.h>
-/* Cadence UART wait UART to be ready to transmit
+/*
+ * Cadence UART wait UART to be ready to transmit
* xb: register which contains the UART base address
- * c: scratch register number */
+ * c: scratch register number
+ */
.macro early_uart_ready xb, c
1:
ldrh w\c, [\xb, #R_UART_SR]
b.ne 1b
.endm
-/* Cadence UART transmit character
+/*
+ * Cadence UART transmit character
* xb: register which contains the UART base address
- * wt: register which contains the character to transmit */
+ * wt: register which contains the character to transmit
+ */
.macro early_uart_transmit xb, wt
strb \wt, [\xb, #R_UART_TX]
.endm
#include <asm/asm_defns.h>
-/* PL011 UART initialization
+/*
+ * PL011 UART initialization
* xb: register which containts the UART base address
- * c: scratch register number */
+ * c: scratch register number
+ */
.macro early_uart_init xb, c
mov x\c, #(7372800 / EARLY_PRINTK_BAUD % 16)
strh w\c, [\xb, #0x28] /* -> UARTFBRD (Baud divisor fraction) */
str w\c, [\xb, #0x30] /* -> UARTCR (Control Register) */
.endm
-/* PL011 UART wait UART to be ready to transmit
+/*
+ * PL011 UART wait UART to be ready to transmit
* xb: register which contains the UART base address
- * c: scratch register number */
+ * c: scratch register number
+ */
.macro early_uart_ready xb, c
1:
ldrh w\c, [\xb, #0x18] /* <- UARTFR (Flag register) */
b.ne 1b /* Wait for the UART to be ready */
.endm
-/* PL011 UART transmit character
+/*
+ * PL011 UART transmit character
* xb: register which contains the UART base address
- * wt: register which contains the character to transmit */
+ * wt: register which contains the character to transmit
+ */
.macro early_uart_transmit xb, wt
strb \wt, [\xb] /* -> UARTDR (Data Register) */
.endm
#include EARLY_PRINTK_INC
#endif
-/* Print a character on the UART - this function is called by C
- * x0: character to print */
+/*
+ * Print a character on the UART - this function is called by C
+ * x0: character to print
+ */
GLOBAL(early_putch)
ldr x15, =EARLY_UART_VIRTUAL_ADDRESS
early_uart_ready x15, 1
/*
* Register aliases.
*/
-lr .req x30 // link register
+lr .req x30 /* link register */
/*
* Stack pushing/popping (register pairs only). Equivalent to store decrement
return_from_trap:
msr daifset, #2 /* Mask interrupts */
- ldr x21, [sp, #UREGS_PC] // load ELR
- ldr w22, [sp, #UREGS_CPSR] // load SPSR
+ ldr x21, [sp, #UREGS_PC] /* load ELR */
+ ldr w22, [sp, #UREGS_CPSR] /* load SPSR */
pop x0, x1
pop x2, x3
pop x6, x7
pop x8, x9
- msr elr_el2, x21 // set up the return data
+ msr elr_el2, x21 /* set up the return data */
msr spsr_el2, x22
pop x10, x11
.align 11
ENTRY(hyp_traps_vector)
- ventry hyp_sync_invalid // Synchronous EL2t
- ventry hyp_irq_invalid // IRQ EL2t
- ventry hyp_fiq_invalid // FIQ EL2t
- ventry hyp_error_invalid // Error EL2t
-
- ventry hyp_sync // Synchronous EL2h
- ventry hyp_irq // IRQ EL2h
- ventry hyp_fiq_invalid // FIQ EL2h
- ventry hyp_error // Error EL2h
-
- ventry guest_sync // Synchronous 64-bit EL0/EL1
- ventry guest_irq // IRQ 64-bit EL0/EL1
- ventry guest_fiq_invalid // FIQ 64-bit EL0/EL1
- ventry guest_error // Error 64-bit EL0/EL1
-
- ventry guest_sync_compat // Synchronous 32-bit EL0/EL1
- ventry guest_irq_compat // IRQ 32-bit EL0/EL1
- ventry guest_fiq_invalid_compat // FIQ 32-bit EL0/EL1
- ventry guest_error_compat // Error 32-bit EL0/EL1
+ ventry hyp_sync_invalid /* Synchronous EL2t */
+ ventry hyp_irq_invalid /* IRQ EL2t */
+ ventry hyp_fiq_invalid /* FIQ EL2t */
+ ventry hyp_error_invalid /* Error EL2t */
+
+ ventry hyp_sync /* Synchronous EL2h */
+ ventry hyp_irq /* IRQ EL2h */
+ ventry hyp_fiq_invalid /* FIQ EL2h */
+ ventry hyp_error /* Error EL2h */
+
+ ventry guest_sync /* Synchronous 64-bit EL0/EL1 */
+ ventry guest_irq /* IRQ 64-bit EL0/EL1 */
+ ventry guest_fiq_invalid /* FIQ 64-bit EL0/EL1 */
+ ventry guest_error /* Error 64-bit EL0/EL1 */
+
+ ventry guest_sync_compat /* Synchronous 32-bit EL0/EL1 */
+ ventry guest_irq_compat /* IRQ 32-bit EL0/EL1 */
+ ventry guest_fiq_invalid_compat /* FIQ 32-bit EL0/EL1 */
+ ventry guest_error_compat /* Error 32-bit EL0/EL1 */
/*
* struct vcpu *__context_switch(struct vcpu *prev, struct vcpu *next)
ENTRY(__context_switch)
add x8, x0, #VCPU_arch_saved_context
mov x9, sp
- stp x19, x20, [x8], #16 // store callee-saved registers
+ stp x19, x20, [x8], #16 /* store callee-saved registers */
stp x21, x22, [x8], #16
stp x23, x24, [x8], #16
stp x25, x26, [x8], #16
str lr, [x8]
add x8, x1, #VCPU_arch_saved_context
- ldp x19, x20, [x8], #16 // restore callee-saved registers
+ ldp x19, x20, [x8], #16 /* restore callee-saved registers */
ldp x21, x22, [x8], #16
ldp x23, x24, [x8], #16
ldp x25, x26, [x8], #16
projects / people / dariof / xen.git / commitdiff