* BIOS has programmed on AP based on BSP's info we saved (since BIOS
* is required to set the same value for all threads/cores).
*/
- if ( (val & APIC_DM_MASK) != APIC_DM_FIXED
- || (val & APIC_VECTOR_MASK) > 0xf )
+ if ( (val & APIC_DM_MASK) != APIC_DM_FIXED || APIC_VECTOR_VALID(val) )
apic_write(APIC_LVTTHMR, val);
if ( (msr_content & (1ULL<<3))
* will end up back here. Break the cycle by only injecting LVTERR
* if it will succeed, and folding in RECVILL otherwise.
*/
- if ( (lvterr & APIC_VECTOR_MASK) >= 16 )
+ if ( APIC_VECTOR_VALID(lvterr) )
inj = true;
else
set_bit(ilog2(APIC_ESR_RECVILL), &vlapic->hw.pending_esr);
bool vlapic_test_irq(const struct vlapic *vlapic, uint8_t vec)
{
- if ( unlikely(vec < 16) )
+ if ( unlikely(!APIC_VECTOR_VALID(vec)) )
return false;
if ( hvm_funcs.test_pir &&
{
struct vcpu *target = vlapic_vcpu(vlapic);
- if ( unlikely(vec < 16) )
+ if ( unlikely(!APIC_VECTOR_VALID(vec)) )
{
vlapic_error(vlapic, ilog2(APIC_ESR_RECVILL));
return;
struct vlapic *target = vlapic_lowest_prio(
vlapic_domain(vlapic), vlapic, short_hand, dest, dest_mode);
- if ( unlikely((icr_low & APIC_VECTOR_MASK) < 16) )
+ if ( unlikely(!APIC_VECTOR_VALID(icr_low)) )
vlapic_error(vlapic, ilog2(APIC_ESR_SENDILL));
else if ( target )
vlapic_accept_irq(vlapic_vcpu(target), icr_low);
}
case APIC_DM_FIXED:
- if ( unlikely((icr_low & APIC_VECTOR_MASK) < 16) )
+ if ( unlikely(!APIC_VECTOR_VALID(icr_low)) )
{
vlapic_error(vlapic, ilog2(APIC_ESR_SENDILL));
break;
#define APIC_DM_STARTUP 0x00600
#define APIC_DM_EXTINT 0x00700
#define APIC_VECTOR_MASK 0x000FF
+#define APIC_VECTOR_VALID(x) \
+ (((x) & APIC_VECTOR_MASK) >= 16)
#define APIC_ICR2 0x310
#define GET_xAPIC_DEST_FIELD(x) (((x)>>24)&0xFF)
#define SET_xAPIC_DEST_FIELD(x) ((x)<<24)