BaseSynchronizationLib: Fix LoongArch64 synchronization functions

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4432

There is a return value bug:
The sc.w/sc.d instruction will destroy the reg_t0,
use reg_t1 to avoid context reg_t0 being corrupted.
Adjust Check that ptr align is UINT16.
Optimize function SyncIncrement and SyncDecrement.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Chao Li <lichao@loongson.cn>
Signed-off-by: Dongyan Qian <qiandongyan@loongson.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>

diff --git a/MdePkg/Library/BaseSynchronizationLib/LoongArch64/AsmSynchronization.S b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/AsmSynchronization.S
index fdd50c54b5f3769eac3e9a867dd61d72546df5db..03865bf2c9664c03a583d1cc4e877c558e1e22a1 100644 (file)
--- a/MdePkg/Library/BaseSynchronizationLib/LoongArch64/AsmSynchronization.S
+++ b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/AsmSynchronization.S
@@ -53,9 +53,9 @@ ASM_PFX(AsmInternalSyncCompareExchange32):
 1:\r
   ll.w  $t0, $a0, 0x0\r
   bne   $t0, $a1, 2f\r
-  move  $t0, $a2\r
-  sc.w  $t0, $a0, 0x0\r
-  beqz  $t0, 1b\r
+  move  $t1, $a2\r
+  sc.w  $t1, $a0, 0x0\r
+  beqz  $t1, 1b\r
   b     3f\r
 2:\r
   dbar  0\r
@@ -76,9 +76,9 @@ ASM_PFX(AsmInternalSyncCompareExchange64):
 1:\r
   ll.d  $t0, $a0, 0x0\r
   bne   $t0, $a1, 2f\r
-  move  $t0, $a2\r
-  sc.d  $t0, $a0, 0x0\r
-  beqz  $t0, 1b\r
+  move  $t1, $a2\r
+  sc.d  $t1, $a0, 0x0\r
+  beqz  $t1, 1b\r
   b     3f\r
 2:\r
   dbar  0\r
@@ -94,13 +94,10 @@ AsmInternalSyncIncrement (
   )\r
 **/\r
 ASM_PFX(AsmInternalSyncIncrement):\r
-  move     $t0, $a0\r
-  dbar     0\r
-  ld.w     $t1, $t0, 0x0\r
-  li.w     $t2, 1\r
-  amadd.w  $t1, $t2, $t0\r
+  li.w     $t0, 1\r
+  amadd.w  $zero, $t0, $a0\r
 \r
-  ld.w     $a0, $t0, 0x0\r
+  ld.w     $a0, $a0, 0\r
   jirl     $zero, $ra, 0\r
 \r
 /**\r
@@ -111,12 +108,9 @@ AsmInternalSyncDecrement (
   )\r
 **/\r
 ASM_PFX(AsmInternalSyncDecrement):\r
-  move     $t0, $a0\r
-  dbar     0\r
-  ld.w     $t1, $t0, 0x0\r
-  li.w     $t2, -1\r
-  amadd.w  $t1, $t2, $t0\r
+  li.w     $t0, -1\r
+  amadd.w  $zero, $t0, $a0\r
 \r
-  ld.w     $a0, $t0, 0x0\r
+  ld.w     $a0, $a0, 0\r
   jirl     $zero, $ra, 0\r
 .end\r

diff --git a/MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synchronization.c b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synchronization.c
index d696c8ce102fb291ccab99c0e5ff50ac033fe07d..6baf841c9b09846f432cc1734cec9e5185d34683 100644 (file)
--- a/MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synchronization.c
+++ b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synchronization.c
@@ -81,7 +81,7 @@ InternalSyncCompareExchange16 (
   volatile UINT32  *Ptr32;\r
 \r
   /* Check that ptr is naturally aligned */\r
-  ASSERT (!((UINT64)Value & (sizeof (Value) - 1)));\r
+  ASSERT (!((UINT64)Value & (sizeof (UINT16) - 1)));\r
 \r
   /* Mask inputs to the correct size. */\r
   Mask               = (((~0UL) - (1UL << (0)) + 1) & (~0UL >> (64 - 1 - ((sizeof (UINT16) * 8) - 1))));\r