Add more SuperSparcs

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4633 c046a42c-6fe2-441c-8c8c-71466251a162

diff --git a/target-sparc/helper.c b/target-sparc/helper.c
index 4537314d697a53679b83bf715b05627628e561e4..bf74c0d2936a26fc12256bc0163e677ad9f9c50f 100644 (file)
--- a/target-sparc/helper.c
+++ b/target-sparc/helper.c
@@ -1213,6 +1213,30 @@ static const sparc_def_t sparc_defs[] = {
         .mmu_trcr_mask = 0x00ffffff,
         .features = CPU_DEFAULT_FEATURES,
     },
+    {
+        .name = "TI SuperSparc 40", // STP1020NPGA
+        .iu_version = 0x41000000,
+        .fpu_version = 0 << 17,
+        .mmu_version = 0x00000000,
+        .mmu_bm = 0x00002000,
+        .mmu_ctpr_mask = 0xffffffc0,
+        .mmu_cxr_mask = 0x0000ffff,
+        .mmu_sfsr_mask = 0xffffffff,
+        .mmu_trcr_mask = 0xffffffff,
+        .features = CPU_DEFAULT_FEATURES,
+    },
+    {
+        .name = "TI SuperSparc 50", // STP1020PGA
+        .iu_version = 0x40000000,
+        .fpu_version = 0 << 17,
+        .mmu_version = 0x04000000,
+        .mmu_bm = 0x00002000,
+        .mmu_ctpr_mask = 0xffffffc0,
+        .mmu_cxr_mask = 0x0000ffff,
+        .mmu_sfsr_mask = 0xffffffff,
+        .mmu_trcr_mask = 0xffffffff,
+        .features = CPU_DEFAULT_FEATURES,
+    },
     {
         .name = "TI SuperSparc 51",
         .iu_version = 0x43000000,
@@ -1225,6 +1249,18 @@ static const sparc_def_t sparc_defs[] = {
         .mmu_trcr_mask = 0xffffffff,
         .features = CPU_DEFAULT_FEATURES,
     },
+    {
+        .name = "TI SuperSparc 60", // STP1020APGA
+        .iu_version = 0x40000000,
+        .fpu_version = 0 << 17,
+        .mmu_version = 0x03000000,
+        .mmu_bm = 0x00002000,
+        .mmu_ctpr_mask = 0xffffffc0,
+        .mmu_cxr_mask = 0x0000ffff,
+        .mmu_sfsr_mask = 0xffffffff,
+        .mmu_trcr_mask = 0xffffffff,
+        .features = CPU_DEFAULT_FEATURES,
+    },
     {
         .name = "TI SuperSparc 61",
         .iu_version = 0x44000000,