]> xenbits.xensource.com Git - xen.git/commitdiff
x86/cpuid: Infrastructure for leaves 7:1{ecx,edx}
authorAndrew Cooper <andrew.cooper3@citrix.com>
Fri, 28 Oct 2022 10:40:00 +0000 (11:40 +0100)
committerAndrew Cooper <andrew.cooper3@citrix.com>
Thu, 9 Feb 2023 18:26:17 +0000 (18:26 +0000)
We don't actually need ecx yet, but adding it in now will reduce the amount to
which leaf 7 is out of order in a featureset.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
tools/misc/xen-cpuid.c
xen/arch/x86/cpu/common.c
xen/include/public/arch-x86/cpufeatureset.h
xen/include/xen/lib/x86/cpuid.h

index 08831af46c3f1c6114603d95e52d82bd9b28506e..ba749fcb704a9e2791987f575212e25d6c2411be 100644 (file)
@@ -204,6 +204,14 @@ static const char *const str_7b1[32] =
     [ 0] = "ppin",
 };
 
+static const char *const str_7c1[32] =
+{
+};
+
+static const char *const str_7d1[32] =
+{
+};
+
 static const char *const str_7d2[32] =
 {
     [ 0] = "intel-psfd",
@@ -231,6 +239,8 @@ static const struct {
     { "0x80000021.eax",  "e21a", str_e21a },
     { "0x00000007:1.ebx", "7b1", str_7b1 },
     { "0x00000007:2.edx", "7d2", str_7d2 },
+    { "0x00000007:1.ecx", "7c1", str_7c1 },
+    { "0x00000007:1.edx", "7d1", str_7d1 },
 };
 
 #define COL_ALIGN "18"
index f44c907e8a431caad95aacab58fd3180e38abcd5..860f2dea5c7dd8b598686085828f4a019d968112 100644 (file)
@@ -453,7 +453,8 @@ static void generic_identify(struct cpuinfo_x86 *c)
                        cpuid_count(7, 1,
                                    &c->x86_capability[FEATURESET_7a1],
                                    &c->x86_capability[FEATURESET_7b1],
-                                   &tmp, &tmp);
+                                   &c->x86_capability[FEATURESET_7c1],
+                                   &c->x86_capability[FEATURESET_7d1]);
                if (max_subleaf >= 2)
                        cpuid_count(7, 2,
                                    &tmp, &tmp, &tmp,
index 3b85bcca153787d21e781ea49c703bf55c4695d1..9fb19b7057b58a6359e69dc95804941027ac8fe9 100644 (file)
@@ -297,6 +297,10 @@ XEN_CPUFEATURE(RRSBA_CTRL,         13*32+ 2) /*   MSR_SPEC_CTRL.RRSBA_DIS_* */
 XEN_CPUFEATURE(BHI_CTRL,           13*32+ 4) /*   MSR_SPEC_CTRL.BHI_DIS_S */
 XEN_CPUFEATURE(MCDT_NO,            13*32+ 5) /*A  MCDT_NO */
 
+/* Intel-defined CPU features, CPUID level 0x00000007:1.ecx, word 14 */
+
+/* Intel-defined CPU features, CPUID level 0x00000007:1.edx, word 15 */
+
 #endif /* XEN_CPUFEATURE */
 
 /* Clean up from a default include.  Close the enum (for C). */
index 73a5c330365ea051201fde8db3a486f02769cf15..fa98b371eef45077bf9bf379b24aaf99bf049698 100644 (file)
@@ -18,6 +18,8 @@
 #define FEATURESET_e21a  11 /* 0x80000021.eax      */
 #define FEATURESET_7b1   12 /* 0x00000007:1.ebx    */
 #define FEATURESET_7d2   13 /* 0x00000007:2.edx    */
+#define FEATURESET_7c1   14 /* 0x00000007:1.ecx    */
+#define FEATURESET_7d1   15 /* 0x00000007:1.edx    */
 
 struct cpuid_leaf
 {
@@ -194,7 +196,14 @@ struct cpuid_policy
                 uint32_t _7b1;
                 struct { DECL_BITFIELD(7b1); };
             };
-            uint32_t /* c */:32, /* d */:32;
+            union {
+                uint32_t _7c1;
+                struct { DECL_BITFIELD(7c1); };
+            };
+            union {
+                uint32_t _7d1;
+                struct { DECL_BITFIELD(7d1); };
+            };
 
             /* Subleaf 2. */
             uint32_t /* a */:32, /* b */:32, /* c */:32;
@@ -343,6 +352,8 @@ static inline void cpuid_policy_to_featureset(
     fs[FEATURESET_e21a] = p->extd.e21a;
     fs[FEATURESET_7b1] = p->feat._7b1;
     fs[FEATURESET_7d2] = p->feat._7d2;
+    fs[FEATURESET_7c1] = p->feat._7c1;
+    fs[FEATURESET_7d1] = p->feat._7d1;
 }
 
 /* Fill in a CPUID policy from a featureset bitmap. */
@@ -363,6 +374,8 @@ static inline void cpuid_featureset_to_policy(
     p->extd.e21a  = fs[FEATURESET_e21a];
     p->feat._7b1  = fs[FEATURESET_7b1];
     p->feat._7d2  = fs[FEATURESET_7d2];
+    p->feat._7c1  = fs[FEATURESET_7c1];
+    p->feat._7d1  = fs[FEATURESET_7d1];
 }
 
 static inline uint64_t cpuid_policy_xcr0_max(const struct cpuid_policy *p)