x86/spec-ctrl: CPUID/MSR definitions for L1D_FLUSH

This is part of XSA-273 / CVE-2018-3646.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
(cherry picked from commit 3563fc2b2731a63fd7e8372ab0f5cef205bf8477)

diff --git a/docs/misc/xen-command-line.markdown b/docs/misc/xen-command-line.markdown
index f18c7f6e0c9f0ba02149a61af30d973802c3231d..4b6532e99bc065bc8e7b91d5bf70ad9873b8445c 100644 (file)
--- a/docs/misc/xen-command-line.markdown
+++ b/docs/misc/xen-command-line.markdown
@@ -440,10 +440,10 @@ accounting for hardware capabilities as enumerated via CPUID.
 
 Currently accepted:
 
-The Speculation Control hardware features `ibrsb`, `stibp`, `ibpb`, `ssbd` are
-used by default if available and applicable.  They can be ignored,
-e.g. `no-ibrsb`, at which point Xen won't use them itself, and won't offer
-them to guests.
+The Speculation Control hardware features `ibrsb`, `stibp`, `ibpb`,
+`l1d-flush` and `ssbd` are used by default if available and applicable.  They can
+be ignored, e.g. `no-ibrsb`, at which point Xen won't use them itself, and
+won't offer them to guests.
 
 ### cpuid\_mask\_cpu (AMD only)
 > `= fam_0f_rev_c | fam_0f_rev_d | fam_0f_rev_e | fam_0f_rev_f | fam_0f_rev_g | fam_10_rev_b | fam_10_rev_c | fam_11_rev_b`

diff --git a/tools/libxl/libxl_cpuid.c b/tools/libxl/libxl_cpuid.c
index 6a28fec97f191acc9aa509d3fc379b10d02247a9..3d5bc33002373b5e798f17418ada651336634eb0 100644 (file)
--- a/tools/libxl/libxl_cpuid.c
+++ b/tools/libxl/libxl_cpuid.c
@@ -160,6 +160,7 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str)
         {"fpu",          0x00000001, NA, CPUID_REG_EDX,  0,  1},
         {"ibrsb",        0x00000007,  0, CPUID_REG_EDX, 26,  1},
         {"stibp",        0x00000007,  0, CPUID_REG_EDX, 27,  1},
+        {"l1d-flush",    0x00000007,  0, CPUID_REG_EDX, 28,  1},
         {"ssbd",         0x00000007,  0, CPUID_REG_EDX, 31,  1},
         {"topoext",      0x80000001, NA, CPUID_REG_ECX, 22,  1},
         {"tbm",          0x80000001, NA, CPUID_REG_ECX, 21,  1},

diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c
index 24aad999c2badb0187ba77a97e53ab4d9aea6e15..a9ec57ecc66a698b75124b3b4b4484535b381db7 100644 (file)
--- a/xen/arch/x86/setup.c
+++ b/xen/arch/x86/setup.c
@@ -148,6 +148,11 @@ static int __init parse_xen_cpuid(const char *s)
             if ( !val )
                 setup_clear_cpu_cap(X86_FEATURE_SSBD);
         }
+        else if ( (val = parse_boolean("l1d-flush", s, ss)) >= 0 )
+        {
+            if ( !val )
+                setup_clear_cpu_cap(X86_FEATURE_L1D_FLUSH);
+        }
         else
             rc = -EINVAL;
 

diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c
index 97a94621d15b492394bdf03ec66307eca101ac6c..5b839022b1706debab11edf7ca10f452d129ad4c 100644 (file)
--- a/xen/arch/x86/spec_ctrl.c
+++ b/xen/arch/x86/spec_ctrl.c
@@ -249,14 +249,16 @@ static void __init print_details(enum ind_thunk thunk, uint64_t caps)
     printk("Speculative mitigation facilities:\n");
 
     /* Hardware features which pertain to speculative mitigations. */
-    printk("  Hardware features:%s%s%s%s%s%s%s%s\n",
+    printk("  Hardware features:%s%s%s%s%s%s%s%s%s%s\n",
            (_7d0 & cpufeat_mask(X86_FEATURE_IBRSB)) ? " IBRS/IBPB" : "",
            (_7d0 & cpufeat_mask(X86_FEATURE_STIBP)) ? " STIBP"     : "",
+           (_7d0 & cpufeat_mask(X86_FEATURE_L1D_FLUSH)) ? " L1D_FLUSH" : "",
            (_7d0 & cpufeat_mask(X86_FEATURE_SSBD))  ? " SSBD"      : "",
            (e8b  & cpufeat_mask(X86_FEATURE_IBPB))  ? " IBPB"      : "",
            (caps & ARCH_CAPABILITIES_IBRS_ALL)      ? " IBRS_ALL"  : "",
            (caps & ARCH_CAPABILITIES_RDCL_NO)       ? " RDCL_NO"   : "",
            (caps & ARCH_CAPS_RSBA)                  ? " RSBA"      : "",
+           (caps & ARCH_CAPS_SKIP_L1DFL)            ? " SKIP_L1DFL": "",
            (caps & ARCH_CAPS_SSB_NO)                ? " SSB_NO"    : "");
 
 #if defined(CONFIG_INDIRECT_THUNK) || defined(CONFIG_SHADOW_PAGING)

diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h
index 8cbd37a742a08cc6cd2367866473ada2dfb8f2d6..eb5a5f193cd48b3fbda1f92a630bbd900d81511e 100644 (file)
--- a/xen/include/asm-x86/cpufeature.h
+++ b/xen/include/asm-x86/cpufeature.h
@@ -171,6 +171,7 @@
 /* Intel-defined CPU features, CPUID level 0x00000007:0.edx, word 9 */
 #define X86_FEATURE_IBRSB      (9*32+26) /* IBRS and IBPB support (used by Intel) */
 #define X86_FEATURE_STIBP      (9*32+27) /* STIBP */
+#define X86_FEATURE_L1D_FLUSH  (9*32+28) /* MSR_FLUSH_CMD and L1D flush */
 #define X86_FEATURE_ARCH_CAPS  (9*32+29) /* IA32_ARCH_CAPABILITIES MSR */
 #define X86_FEATURE_SSBD       (9*32+31) /* MSR_SPEC_CTRL.SSBD available */
 

diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index c21801c1d15cec64a1ba99b7a2ed6ef320a84f10..9620e856459816ab3329d42cb0c527bc69ed37af 100644 (file)
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -44,8 +44,12 @@
 #define ARCH_CAPABILITIES_RDCL_NO      (_AC(1, ULL) << 0)
 #define ARCH_CAPABILITIES_IBRS_ALL     (_AC(1, ULL) << 1)
 #define ARCH_CAPS_RSBA                 (_AC(1, ULL) << 2)
+#define ARCH_CAPS_SKIP_L1DFL           (_AC(1, ULL) << 3)
 #define ARCH_CAPS_SSB_NO               (_AC(1, ULL) << 4)
 
+#define MSR_FLUSH_CMD                  0x0000010b
+#define FLUSH_CMD_L1D                  (_AC(1, ULL) << 0)
+
 /* Intel MSRs. Some also available on other CPUs */
 #define MSR_IA32_PERFCTR0              0x000000c1
 #define MSR_IA32_A_PERFCTR0            0x000004c1