x86/intel: optional build of TSX support

Transactional Synchronization Extensions are supported on certain Intel's
CPUs only, hence can be put under CONFIG_INTEL build option.

The whole TSX support, even if supported by CPU, may need to be disabled via
options, by microcode or through spec-ctrl, depending on a set of specific
conditions. To make sure nothing gets accidentally runtime-broken all
modifications of global TSX configuration variables is secured by #ifdef's,
while variables themselves redefined to 0, so that ones can't mistakenly be
written to.

Signed-off-by: Sergiy Kibrik <Sergiy_Kibrik@epam.com>
Acked-by: Jan Beulich <jbeulich@suse.com>

diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc
index 98a45211556b7acda227df1a8d23155db6a31278..0a66e1ee2d7e54d99cfb040cdcc979d6d742eddb 100644 (file)
--- a/docs/misc/xen-command-line.pandoc
+++ b/docs/misc/xen-command-line.pandoc
@@ -2586,7 +2586,7 @@ pages) must also be specified via the tbuf_size parameter.
 ### tsx
     = <bool>
 
-    Applicability: x86
+    Applicability: x86 with CONFIG_INTEL active
     Default: false on parts vulnerable to TAA, true otherwise
 
 Controls for the use of Transactional Synchronization eXtensions.

diff --git a/xen/arch/x86/Makefile b/xen/arch/x86/Makefile
index d902fb7accd98cd7a85afdf057cc753ae64271a5..286c003ec3b30d00a9a1508e15d566d45d83c458 100644 (file)
--- a/xen/arch/x86/Makefile
+++ b/xen/arch/x86/Makefile
@@ -67,7 +67,7 @@ obj-y += srat.o
 obj-y += string.o
 obj-y += time.o
 obj-y += traps.o
-obj-y += tsx.o
+obj-$(CONFIG_INTEL) += tsx.o
 obj-y += usercopy.o
 obj-y += x86_emulate.o
 obj-$(CONFIG_TBOOT) += tboot.o

diff --git a/xen/arch/x86/include/asm/processor.h b/xen/arch/x86/include/asm/processor.h
index c26ef9090c3afd24034241755dedb9495131bcb0..66463f6a6d67b1401851c3bd56abb89b306d5ec7 100644 (file)
--- a/xen/arch/x86/include/asm/processor.h
+++ b/xen/arch/x86/include/asm/processor.h
@@ -503,9 +503,15 @@ static inline uint8_t get_cpu_family(uint32_t raw, uint8_t *model,
     return fam;
 }
 
+#ifdef CONFIG_INTEL
 extern int8_t opt_tsx;
 extern bool rtm_disabled;
 void tsx_init(void);
+#else
+#define opt_tsx      0     /* explicitly indicate TSX is off */
+#define rtm_disabled false /* RTM was not force-disabled */
+static inline void tsx_init(void) {}
+#endif
 
 void update_mcu_opt_ctrl(void);
 void set_in_mcu_opt_ctrl(uint32_t mask, uint32_t val);

diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c
index 40f6ae017010a310be54dfdf24a2147124a461fa..6b3631e3753c1128be51db61dc9f4d21b65bc636 100644 (file)
--- a/xen/arch/x86/spec_ctrl.c
+++ b/xen/arch/x86/spec_ctrl.c
@@ -116,8 +116,10 @@ static int __init cf_check parse_spec_ctrl(const char *s)
             if ( opt_pv_l1tf_domu < 0 )
                 opt_pv_l1tf_domu = 0;
 
+#ifdef CONFIG_INTEL
             if ( opt_tsx == -1 )
                 opt_tsx = -3;
+#endif
 
         disable_common:
             opt_rsb_pv = false;
@@ -2264,6 +2266,7 @@ void __init init_speculation_mitigations(void)
      * plausibly value TSX higher than Hyperthreading...), disable TSX to
      * mitigate TAA.
      */
+#ifdef CONFIG_INTEL
     if ( opt_tsx == -1 && cpu_has_bug_taa && cpu_has_tsx_ctrl &&
          ((hw_smt_enabled && opt_smt) ||
           !boot_cpu_has(X86_FEATURE_SC_VERW_IDLE)) )
@@ -2271,6 +2274,7 @@ void __init init_speculation_mitigations(void)
         opt_tsx = 0;
         tsx_init();
     }
+#endif
 
     /*
      * On some SRBDS-affected hardware, it may be safe to relax srb-lock by