if ( !fs_gs_done && !compat )
{
- wrfsbase(n->arch.pv.fs_base);
- wrgsshadow(n->arch.pv.gs_base_kernel);
- wrgsbase(n->arch.pv.gs_base_user);
+ write_fs_base(n->arch.pv.fs_base);
+ write_gs_shadow(n->arch.pv.gs_base_kernel);
+ write_gs_base(n->arch.pv.gs_base_user);
/* If in kernel mode then switch the GS bases around. */
if ( (n->arch.flags & TF_kernel_mode) )
if ( !is_pv_32bit_vcpu(v) )
{
- unsigned long gs_base = rdgsbase();
+ unsigned long gs_base = read_gs_base();
- v->arch.pv.fs_base = rdfsbase();
+ v->arch.pv.fs_base = read_fs_base();
if ( v->arch.flags & TF_kernel_mode )
v->arch.pv.gs_base_kernel = gs_base;
else
* We cannot cache SHADOW_GS_BASE while the VCPU runs, as it can
* be updated at any time via SWAPGS, which we cannot trap.
*/
- v->arch.hvm.vmx.shadow_gs = rdgsshadow();
+ v->arch.hvm.vmx.shadow_gs = read_gs_shadow();
}
static void vmx_restore_guest_msrs(struct vcpu *v)
{
- wrgsshadow(v->arch.hvm.vmx.shadow_gs);
+ write_gs_shadow(v->arch.hvm.vmx.shadow_gs);
wrmsrl(MSR_STAR, v->arch.hvm.vmx.star);
wrmsrl(MSR_LSTAR, v->arch.hvm.vmx.lstar);
wrmsrl(MSR_SYSCALL_MASK, v->arch.hvm.vmx.sfmask);
break;
case MSR_SHADOW_GS_BASE:
- *msr_content = rdgsshadow();
+ *msr_content = read_gs_shadow();
break;
case MSR_STAR:
else if ( msr == MSR_GS_BASE )
__vmwrite(GUEST_GS_BASE, msr_content);
else
- wrgsshadow(msr_content);
+ write_gs_shadow(msr_content);
break;
* Update the cached value of the GS base about to become inactive, as a
* subsequent context switch won't bother re-reading it.
*/
- gs_base = rdgsbase();
+ gs_base = read_gs_base();
if ( v->arch.flags & TF_kernel_mode )
v->arch.pv.gs_base_kernel = gs_base;
else
reg->base = 0;
break;
case x86_seg_fs:
- reg->base = rdfsbase();
+ reg->base = read_fs_base();
break;
case x86_seg_gs:
- reg->base = rdgsbase();
+ reg->base = read_gs_base();
break;
}
case MSR_FS_BASE:
if ( is_pv_32bit_domain(currd) )
break;
- *val = rdfsbase();
+ *val = read_fs_base();
return X86EMUL_OKAY;
case MSR_GS_BASE:
if ( is_pv_32bit_domain(currd) )
break;
- *val = rdgsbase();
+ *val = read_gs_base();
return X86EMUL_OKAY;
case MSR_SHADOW_GS_BASE:
case MSR_FS_BASE:
if ( is_pv_32bit_domain(currd) || !is_canonical_address(val) )
break;
- wrfsbase(val);
+ write_fs_base(val);
return X86EMUL_OKAY;
case MSR_GS_BASE:
if ( is_pv_32bit_domain(currd) || !is_canonical_address(val) )
break;
- wrgsbase(val);
+ write_gs_base(val);
return X86EMUL_OKAY;
case MSR_SHADOW_GS_BASE:
if ( is_pv_32bit_domain(currd) || !is_canonical_address(val) )
break;
- wrgsshadow(val);
+ write_gs_shadow(val);
curr->arch.pv.gs_base_user = val;
return X86EMUL_OKAY;
{
case SEGBASE_FS:
if ( is_canonical_address(base) )
- wrfsbase(base);
+ write_fs_base(base);
else
ret = -EINVAL;
break;
case SEGBASE_GS_USER:
if ( is_canonical_address(base) )
{
- wrgsshadow(base);
+ write_gs_shadow(base);
v->arch.pv.gs_base_user = base;
}
else
case SEGBASE_GS_KERNEL:
if ( is_canonical_address(base) )
- wrgsbase(base);
+ write_gs_base(base);
else
ret = -EINVAL;
break;
: [flat] "r" (FLAT_USER_DS32) );
/* Update the cache of the inactive base, as read from the GDT/LDT. */
- v->arch.pv.gs_base_user = rdgsbase();
+ v->arch.pv.gs_base_user = read_gs_base();
asm volatile ( safe_swapgs );
break;
crs[3] = read_cr3();
crs[4] = read_cr4();
read_sregs(regs);
- crs[5] = rdfsbase();
- crs[6] = rdgsbase();
- crs[7] = rdgsshadow();
+ crs[5] = read_fs_base();
+ crs[6] = read_gs_base();
+ crs[7] = read_gs_shadow();
}
static void _show_registers(
return base;
}
-static inline unsigned long rdfsbase(void)
+static inline unsigned long read_fs_base(void)
{
unsigned long base;
return base;
}
-static inline unsigned long rdgsbase(void)
+static inline unsigned long read_gs_base(void)
{
unsigned long base;
return base;
}
-static inline unsigned long rdgsshadow(void)
+static inline unsigned long read_gs_shadow(void)
{
unsigned long base;
return base;
}
-static inline void wrfsbase(unsigned long base)
+static inline void write_fs_base(unsigned long base)
{
if ( read_cr4() & X86_CR4_FSGSBASE )
#ifdef HAVE_AS_FSGSBASE
wrmsrl(MSR_FS_BASE, base);
}
-static inline void wrgsbase(unsigned long base)
+static inline void write_gs_base(unsigned long base)
{
if ( read_cr4() & X86_CR4_FSGSBASE )
#ifdef HAVE_AS_FSGSBASE
wrmsrl(MSR_GS_BASE, base);
}
-static inline void wrgsshadow(unsigned long base)
+static inline void write_gs_shadow(unsigned long base)
{
if ( read_cr4() & X86_CR4_FSGSBASE )
{