plat/common: Fix cache policy MAIR definitions

Fix transposed cache attributes in MAIR_ATTR for ARM64

Signed-off-by: Michalis Pappas <Michalis.Pappas@opensynergy.com>
Acked-by: Renê de Souza Pinto <Rene.deSouzaPinto@opensynergy.com>
Reviewed-by: Răzvan Vîrtan <virtanrazvan@gmail.com>
Tested-by: Unikraft CI <monkey@unikraft.io>
GitHub-Pull-Request: #170

diff --git a/plat/common/include/arm/arm64/cpu_defs.h b/plat/common/include/arm/arm64/cpu_defs.h
index 53be825eb7409957ad1b71065534ea49b5069f32..7d87f7c0b0853f882ef9dbe21ec3220ff2843131 100644 (file)
--- a/plat/common/include/arm/arm64/cpu_defs.h
+++ b/plat/common/include/arm/arm64/cpu_defs.h
@@ -89,8 +89,8 @@
                MAIR_ATTR(MAIR_DEVICE_nGnRE, DEVICE_nGnRE) |   \
                MAIR_ATTR(MAIR_DEVICE_GRE, DEVICE_GRE) |       \
                MAIR_ATTR(MAIR_NORMAL_NC, NORMAL_NC) |         \
-               MAIR_ATTR(MAIR_NORMAL_WB, NORMAL_WT) |         \
-               MAIR_ATTR(MAIR_NORMAL_WT, NORMAL_WB))
+               MAIR_ATTR(MAIR_NORMAL_WT, NORMAL_WT) |         \
+               MAIR_ATTR(MAIR_NORMAL_WB, NORMAL_WB))
 
 /* TCR_EL1 - Translation Control Register */
 #define TCR_ASID_16    (1 << 36)