}
/* Allocate TX rings - 4 for QoS purposes, 1 for commands. */
- for (i = 0; i < WPI_NTXQUEUES; i++) {
+ for (i = 0; i < WPI_DRV_NTXQUEUES; i++) {
if ((error = wpi_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) {
device_printf(dev,
"could not allocate TX ring %d, error %d\n", i,
if (sc->txq[0].data_dmat) {
/* Free DMA resources. */
- for (qid = 0; qid < WPI_NTXQUEUES; qid++)
+ for (qid = 0; qid < WPI_DRV_NTXQUEUES; qid++)
wpi_free_tx_ring(sc, &sc->txq[qid]);
wpi_free_rx_ring(sc);
bus_dmamap_sync(sc->shared_dma.tag, sc->shared_dma.map,
BUS_DMASYNC_PREWRITE);
- /*
- * We only use rings 0 through 4 (4 EDCA + cmd) so there is no need
- * to allocate commands space for other rings.
- * XXX Do we really need to allocate descriptors for other rings?
- */
- if (qid > WPI_CMD_QUEUE_NUM) {
- DPRINTF(sc, WPI_DEBUG_TRACE, TRACE_STR_END, __func__);
- return 0;
- }
-
size = WPI_TX_RING_COUNT * sizeof (struct wpi_tx_cmd);
error = wpi_dma_contig_alloc(sc, &ring->cmd_dma, (void **)&ring->cmd,
size, 4);
wpi_reset_rx_ring(sc);
/* Reset all TX rings. */
- for (qid = 0; qid < WPI_NTXQUEUES; qid++)
+ for (qid = 0; qid < WPI_DRV_NTXQUEUES; qid++)
wpi_reset_tx_ring(sc, &sc->txq[qid]);
if (wpi_nic_lock(sc) == 0) {