drm/amd/display: allow psr-su/replay for z8

[why]
allow psr-su/replay for z8

Reviewed-by: Muhammad Ahmed <ahmed.ahmed@amd.com>
Reviewed-by: Sung joon Kim <sungjoon.kim@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
index a07f7e685d2890dc7aa50fa0cda8fc6256c156c0..9e588c56c5709b32a5947702421cc2fcb291e7ec 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
@@ -361,32 +361,32 @@ void dcn35_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zst
        case DCN_ZSTATE_SUPPORT_ALLOW:
                msg_id = VBIOSSMC_MSG_AllowZstatesEntry;
                param = (1 << 10) | (1 << 9) | (1 << 8);
-               smu_print("%s: SMC_MSG_AllowZstatesEntry msg = ALLOW, param = %d\n", __func__, param);
+               smu_print("%s: SMC_MSG_AllowZstatesEntry msg = ALLOW, param = 0x%x\n", __func__, param);
                break;
 
        case DCN_ZSTATE_SUPPORT_DISALLOW:
                msg_id = VBIOSSMC_MSG_AllowZstatesEntry;
                param = 0;
-               smu_print("%s: SMC_MSG_AllowZstatesEntry msg_id = DISALLOW, param = %d\n",  __func__, param);
+               smu_print("%s: SMC_MSG_AllowZstatesEntry msg_id = DISALLOW, param = 0x%x\n",  __func__, param);
                break;
 
 
        case DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY:
                msg_id = VBIOSSMC_MSG_AllowZstatesEntry;
                param = (1 << 10);
-               smu_print("%s: SMC_MSG_AllowZstatesEntry msg = ALLOW_Z10_ONLY, param = %d\n", __func__, param);
+               smu_print("%s: SMC_MSG_AllowZstatesEntry msg = ALLOW_Z10_ONLY, param = 0x%x\n", __func__, param);
                break;
 
        case DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY:
                msg_id = VBIOSSMC_MSG_AllowZstatesEntry;
                param = (1 << 10) | (1 << 8);
-               smu_print("%s: SMC_MSG_AllowZstatesEntry msg = ALLOW_Z8_Z10_ONLY, param = %d\n", __func__, param);
+               smu_print("%s: SMC_MSG_AllowZstatesEntry msg = ALLOW_Z8_Z10_ONLY, param = 0x%x\n", __func__, param);
                break;
 
        case DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY:
                msg_id = VBIOSSMC_MSG_AllowZstatesEntry;
                param = (1 << 8);
-               smu_print("%s: SMC_MSG_AllowZstatesEntry msg = ALLOW_Z8_ONLY, param = %d\n", __func__, param);
+               smu_print("%s: SMC_MSG_AllowZstatesEntry msg = ALLOW_Z8_ONLY, param = 0x%x\n", __func__, param);
                break;
 
        default: //DCN_ZSTATE_SUPPORT_UNKNOWN
@@ -400,7 +400,7 @@ void dcn35_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zst
                clk_mgr,
                msg_id,
                param);
-       smu_print("%s:  msg_id = %d, param = 0x%x, return = %d\n", __func__, msg_id, param, retv);
+       smu_print("%s:  msg_id = %d, param = 0x%x, return = 0x%x\n", __func__, msg_id, param, retv);
 }
 
 int dcn35_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
index 912256006d7567a712ca191346389cd9f10ac974..80bebfc268db0f59d2ac9067d3780f6675760afb 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
@@ -588,7 +588,9 @@ void dcn35_decide_zstate_support(struct dc *dc, struct dc_state *context)
        } else if (context->stream_count == 1 && context->streams[0]->signal == SIGNAL_TYPE_EDP) {
                struct dc_link *link = context->streams[0]->sink->link;
                bool is_pwrseq0 = link && link->link_index == 0;
-               bool is_psr1 = link && link->psr_settings.psr_version == DC_PSR_VERSION_1 && !link->panel_config.psr.disable_psr;
+               bool is_psr = (link && (link->psr_settings.psr_version == DC_PSR_VERSION_1 ||
+                                                               link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) && !link->panel_config.psr.disable_psr);
+               bool is_replay = link && link->replay_settings.replay_feature_enabled;
                int minmum_z8_residency =
                        dc->debug.minimum_z8_residency_time > 0 ? dc->debug.minimum_z8_residency_time : 1000;
                bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency;
@@ -596,12 +598,14 @@ void dcn35_decide_zstate_support(struct dc *dc, struct dc_state *context)
                        dc->debug.minimum_z10_residency_time > 0 ? dc->debug.minimum_z10_residency_time : 5000;
                bool allow_z10 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z10_residency;
 
+               /*for psr1/psr-su, we allow z8 and z10 based on latency, for replay with IPS enabled, it will enter ips2*/
                if (is_pwrseq0 && allow_z10)
                        support = DCN_ZSTATE_SUPPORT_ALLOW;
-               else if (is_pwrseq0 && is_psr1)
+               else if (is_pwrseq0 && (is_psr || is_replay))
                        support = allow_z8 ? DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY : DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY;
                else if (allow_z8)
                        support = DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY;
+
        }
 
        context->bw_ctx.bw.dcn.clk.zstate_support = support;