drm/i915: Add Wa_18028616096

Drop UGM per set fragment threshold to 3

BSpec: 54833
Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
[mattrope: moved above xehpsdv block for consistency]
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230922155356.583595-1-shekhar.chauhan@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 9f2a7d103ea5dd02d22bbb65c7310a35b35633b3..cca4bac8f8b05c7debf386822a93fb8052bf5758 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1232,6 +1232,7 @@
 #define   DISABLE_D8_D16_COASLESCE             REG_BIT(30)
 #define   FORCE_1_SUB_MESSAGE_PER_FRAGMENT     REG_BIT(15)
 #define LSC_CHICKEN_BIT_0_UDW                  MCR_REG(0xe7c8 + 4)
+#define   UGM_FRAGMENT_THRESHOLD_TO_3          REG_BIT(58 - 32)
 #define   DIS_CHAIN_2XSIMD8                    REG_BIT(55 - 32)
 #define   FORCE_SLM_FENCE_SCOPE_TO_TILE                REG_BIT(42 - 32)
 #define   FORCE_UGM_FENCE_SCOPE_TO_TILE                REG_BIT(41 - 32)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index fcde2e1562ab8c70eab764322f92b6d43f0985f9..0ddddccc435450aa484feba338d9cdc4b881dde7 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2941,6 +2941,11 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
                           true);
        }
 
+       if (IS_DG2_G10(i915) || IS_DG2_G12(i915)) {
+               /* Wa_18028616096 */
+               wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3);
+       }
+
        if (IS_XEHPSDV(i915)) {
                /* Wa_1409954639 */
                wa_mcr_masked_en(wal,