plat/kvm/x86: Don't create fine-grained mapping for low memory

Mapping all memory makes the page table more independent of the actual
boot protocol. Firecracker currently puts the protocol information at a
very low address (0x7000).

Signed-off-by: Marco Schlumpp <marco@unikraft.io>
Reviewed-by: Sergiu Moga <sergiu.moga@protonmail.com>
Approved-by: Marc Rittinghaus <marc.rittinghaus@unikraft.io>
Tested-by: Unikraft CI <monkey@unikraft.io>
GitHub-Closes: #760

diff --git a/plat/kvm/x86/pagetable64.S b/plat/kvm/x86/pagetable64.S
index 39ae2b065a87fb768fd2e52f43735ace1e15a2f2..bc3f49ca9fa93cfd5b0edcb2df23d2ae3689a9d5 100644 (file)
--- a/plat/kvm/x86/pagetable64.S
+++ b/plat/kvm/x86/pagetable64.S
@@ -121,30 +121,12 @@
  *
  * 0x0000000000000000 - 0x00000000ffffffff Mapping of first 4GB
  *
- * However, the first 1M is inaccessible, except for:
- * 0x0000000000008000 - 0x0000000000008fff 16-bit entry code (read+write)
- * 0x0000000000009000 - 0x0000000000009fff Multiboot info @ 0x09500 (read-only)
- * 0x00000000000b8000 - 0x00000000000bffff VGA buffer (read+write)
- * 0x00000000000e0000 - 0x00000000000fffff BIOS memory (read-only)
- *
  * If paging is enabled:
  * 0xffffff8000000000 - 0xffffffffffffffff Mapping of first 512GB (for PTs)
  */
 .align 0x1000
-x86_bpt_pt0_0_0: /* 4K pages */
-       pte_zero 0x0000000000000000, 0x008
-       pte_fill 0x0000000000008000, 0x001, PT_LVL, PTE_RW
-       pte_fill 0x0000000000009000, 0x008, PT_LVL, PTE_RO
-       pte_zero 0x0000000000010000, 0x0a7
-       pte_fill 0x00000000000b8000, 0x008, PT_LVL, PTE_RW
-       pte_zero 0x00000000000c0000, 0x020
-       pte_fill 0x00000000000e0000, 0x020, PT_LVL, PTE_RO
-       pte_fill 0x0000000000100000, 0x100, PT_LVL, PTE_RW
-
-.align 0x1000
 x86_bpt_pd0_0: /* 2M pages */
-       pte      x86_bpt_pt0_0_0, PTE_RW
-       pte_fill 0x0000000000200000, 0x1ff, PD_LVL, PTE_RW
+       pte_fill 0x0000000000000000, 0x200, PD_LVL, PTE_RW
 
 x86_bpt_pd0_1: /* 2M pages */
        pte_fill 0x0000000040000000, 0x200, PD_LVL, PTE_RW