if ( cpu_has_smap )
set_in_cr4(X86_CR4_SMAP);
- cr4_pv32_mask = mmu_cr4_features & (X86_CR4_SMEP | X86_CR4_SMAP);
+ cr4_pv32_mask = mmu_cr4_features & XEN_CR4_PV32_BITS;
if ( cpu_has_fsgsbase )
set_in_cr4(X86_CR4_FSGSBASE);
push %rdx
GET_CPUINFO_FIELD(cr4, dx)
mov (%rdx), %rax
- test $X86_CR4_SMEP|X86_CR4_SMAP,%eax
+ test $XEN_CR4_PV32_BITS, %eax
jnz 0f
or cr4_pv32_mask(%rip), %rax
mov %rax, %cr4
#ifndef NDEBUG
/* Check that _all_ of the bits intended to be set actually are. */
mov %cr4, %rax
- and cr4_pv32_mask(%rip), %eax
- cmp cr4_pv32_mask(%rip), %eax
+ and cr4_pv32_mask(%rip), %rax
+ cmp cr4_pv32_mask(%rip), %rax
je 1f
+ /* Cause cr4_pv32_mask to be visible in the BUG register dump. */
+ mov cr4_pv32_mask(%rip), %rdx
BUG
1:
#endif
#define XEN_MINIMAL_CR4 (X86_CR4_PGE | X86_CR4_PAE)
+#define XEN_CR4_PV32_BITS (X86_CR4_SMEP|X86_CR4_SMAP)
+
#define XEN_SYSCALL_MASK (X86_EFLAGS_AC|X86_EFLAGS_VM|X86_EFLAGS_RF| \
X86_EFLAGS_NT|X86_EFLAGS_DF|X86_EFLAGS_IF| \
X86_EFLAGS_TF)