media: cedrus: h265: Fix configuring bitstream size

[ Upstream commit 3a11887f7f11a6bb1f05e7f67b3ea20dadfec443 ]

bit_size field holds size of slice, not slice + header. Because of HW
quirks, driver can't program in just slice, but also preceding header.
But that means that currently used bit_size is wrong (too small).
Instead, just use size of whole buffer. There is no harm in doing this.

Fixes: 86caab29da78 ("media: cedrus: Add HEVC/H.265 decoding support")
Suggested-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c
index 7a438cd22c34184bcc871351f7b65f407e0109a7..9f13c942a806b63e37e0cb493804f40c303a7ee7 100644 (file)
--- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c
+++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c
@@ -414,11 +414,11 @@ static int cedrus_h265_setup(struct cedrus_ctx *ctx, struct cedrus_run *run)
        unsigned int ctb_addr_x, ctb_addr_y;
        struct cedrus_buffer *cedrus_buf;
        dma_addr_t src_buf_addr;
-       dma_addr_t src_buf_end_addr;
        u32 chroma_log2_weight_denom;
        u32 num_entry_point_offsets;
        u32 output_pic_list_index;
        u32 pic_order_cnt[2];
+       size_t slice_bytes;
        u8 padding;
        int count;
        u32 reg;
@@ -430,6 +430,7 @@ static int cedrus_h265_setup(struct cedrus_ctx *ctx, struct cedrus_run *run)
        pred_weight_table = &slice_params->pred_weight_table;
        num_entry_point_offsets = slice_params->num_entry_point_offsets;
        cedrus_buf = vb2_to_cedrus_buffer(&run->dst->vb2_buf);
+       slice_bytes = vb2_get_plane_payload(&run->src->vb2_buf, 0);
 
        /*
         * If entry points offsets are present, we should get them
@@ -477,7 +478,7 @@ static int cedrus_h265_setup(struct cedrus_ctx *ctx, struct cedrus_run *run)
 
        cedrus_write(dev, VE_DEC_H265_BITS_OFFSET, 0);
 
-       reg = slice_params->bit_size;
+       reg = slice_bytes * 8;
        cedrus_write(dev, VE_DEC_H265_BITS_LEN, reg);
 
        /* Source beginning and end addresses. */
@@ -491,10 +492,7 @@ static int cedrus_h265_setup(struct cedrus_ctx *ctx, struct cedrus_run *run)
 
        cedrus_write(dev, VE_DEC_H265_BITS_ADDR, reg);
 
-       src_buf_end_addr = src_buf_addr +
-                          DIV_ROUND_UP(slice_params->bit_size, 8);
-
-       reg = VE_DEC_H265_BITS_END_ADDR_BASE(src_buf_end_addr);
+       reg = VE_DEC_H265_BITS_END_ADDR_BASE(src_buf_addr + slice_bytes);
        cedrus_write(dev, VE_DEC_H265_BITS_END_ADDR, reg);
 
        /* Coding tree block address */