]> xenbits.xensource.com Git - xen.git/commitdiff
x86/spec_ctrl: Elide MSR_SPEC_CTRL handling in idle context when possible
authorAndrew Cooper <andrew.cooper3@citrix.com>
Tue, 29 May 2018 09:00:04 +0000 (11:00 +0200)
committerJan Beulich <jbeulich@suse.com>
Tue, 29 May 2018 09:00:04 +0000 (11:00 +0200)
If Xen is virtualising MSR_SPEC_CTRL handling for guests, but using 0 as its
own MSR_SPEC_CTRL value, spec_ctrl_{enter,exit}_idle() need not write to the
MSR.

Requested-by: Jan Beulich <JBeulich@suse.com>
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Wei Liu <wei.liu2@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
master commit: 94df6e8588e35cc2028ccb3fd2921c6e6360605e
master date: 2018-05-16 12:19:10 +0100

xen/arch/x86/cpu/common.c
xen/arch/x86/spec_ctrl.c
xen/include/asm-x86/cpufeature.h
xen/include/asm-x86/spec_ctrl.h

index 1ba1622e72baa3c4eebe85531573f82e1bcda51e..15e831abde39fb7c79b442c803b888de8290747f 100644 (file)
@@ -368,6 +368,9 @@ void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
                if (test_bit(X86_FEATURE_SC_RSB_HVM,
                             boot_cpu_data.x86_capability))
                        __set_bit(X86_FEATURE_SC_RSB_HVM, c->x86_capability);
+               if (test_bit(X86_FEATURE_SC_MSR_IDLE,
+                            boot_cpu_data.x86_capability))
+                       __set_bit(X86_FEATURE_SC_MSR_IDLE, c->x86_capability);
 
                /* AND the already accumulated flags with these */
                for ( i = 0 ; i < NCAPINTS ; i++ )
index 91e18487f0fc9fa08bfff518e8fe60570799d8eb..778f8e58331dd7f787f8d74bf34b2a572cd6e280 100644 (file)
@@ -324,6 +324,10 @@ void __init init_speculation_mitigations(void)
     /* (Re)init BSP state now that default_spec_ctrl_flags has been calculated. */
     init_shadow_spec_ctrl_state();
 
+    /* If Xen is using any MSR_SPEC_CTRL settings, adjust the idle path. */
+    if ( default_xen_spec_ctrl )
+        __set_bit(X86_FEATURE_SC_MSR_IDLE, boot_cpu_data.x86_capability);
+
     print_details(thunk, caps);
 }
 
index 9c8bca9faab323201bfae036741eec614f97a7b3..d1409827086dccf376f94e6d8e7a5b641066dafd 100644 (file)
@@ -76,6 +76,7 @@
 #define X86_FEATURE_XTOPOLOGY    (3*32+13) /* cpu topology enum extensions */
 #define X86_FEATURE_CPUID_FAULTING (3*32+14) /* cpuid faulting */
 #define X86_FEATURE_CLFLUSH_MONITOR (3*32+15) /* clflush reqd with monitor */
+#define X86_FEATURE_SC_MSR_IDLE     (3*32+16) /* SC_MSR && default_xen_spec_ctrl */
 
 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
 #define X86_FEATURE_XMM3       (4*32+ 0) /* Streaming SIMD Extensions-3 */
index 6c11562f7104a483bceab4a93b0e8730d409070f..ec943e18e306606304fee40fdf71a239d1eb65c5 100644 (file)
@@ -54,7 +54,7 @@ static always_inline void spec_ctrl_enter_idle(struct cpu_info *info)
     barrier();
     asm volatile ( ALTERNATIVE(ASM_NOP3, "wrmsr", %c3)
                    :: "a" (val), "c" (MSR_SPEC_CTRL), "d" (0),
-                      "i" (X86_FEATURE_SC_MSR)
+                      "i" (X86_FEATURE_SC_MSR_IDLE)
                    : "memory" );
 }
 
@@ -71,7 +71,7 @@ static always_inline void spec_ctrl_exit_idle(struct cpu_info *info)
     barrier();
     asm volatile ( ALTERNATIVE(ASM_NOP3, "wrmsr", %c3)
                    :: "a" (val), "c" (MSR_SPEC_CTRL), "d" (0),
-                      "i" (X86_FEATURE_SC_MSR)
+                      "i" (X86_FEATURE_SC_MSR_IDLE)
                    : "memory" );
 }