handle : int array;
}
type sched_control = { weight : int; cap : int; }
+type physinfo_cap_flag = CAP_HVM | CAP_DirectIO
type physinfo = {
nr_cpus : int;
threads_per_core : int;
total_pages : nativeint;
free_pages : nativeint;
scrub_pages : nativeint;
+ capabilities : physinfo_cap_flag list;
}
type version = { major : int; minor : int; extra : string; }
type compile_info = {
CAMLprim value stub_xc_physinfo(value xc_handle)
{
CAMLparam1(xc_handle);
- CAMLlocal1(physinfo);
+ CAMLlocal3(physinfo, cap_list, tmp);
xc_physinfo_t c_physinfo;
int r;
if (r)
failwith_xc();
- physinfo = caml_alloc_tuple(9);
+ tmp = cap_list = Val_emptylist;
+ for (r = 0; r < 2; r++) {
+ if ((c_physinfo.capabilities >> r) & 1) {
+ tmp = caml_alloc_small(2, Tag_cons);
+ Field(tmp, 0) = Val_int(r);
+ Field(tmp, 1) = cap_list;
+ cap_list = tmp;
+ }
+ }
+
+ physinfo = caml_alloc_tuple(10);
Store_field(physinfo, 0, Val_int(COMPAT_FIELD_physinfo_get_nr_cpus(c_physinfo)));
Store_field(physinfo, 1, Val_int(c_physinfo.threads_per_core));
Store_field(physinfo, 2, Val_int(c_physinfo.cores_per_socket));
Store_field(physinfo, 6, caml_copy_nativeint(c_physinfo.total_pages));
Store_field(physinfo, 7, caml_copy_nativeint(c_physinfo.free_pages));
Store_field(physinfo, 8, caml_copy_nativeint(c_physinfo.scrub_pages));
+ Store_field(physinfo, 9, cap_list);
CAMLreturn(physinfo);
}