x86/msr: further correct the emulation behaviour of MSR_PRED_CMD

Following commit a6aa678fa3 ("x86/msr: Correct the emulation behaviour
of MSR_PRED_CMD") we may end up writing the low bit with the wrong
value. While it's unlikely for a guest to want to write zero there, we
should still permit (this without incurring the overhead of an actual
barrier). Correcting this right away will also help whenever further
bits in the MSR might become defined.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
Release-acked-by: Juergen Gross <jgross@suse.com>

diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c
index d0345611c1b3dab4e1b9193d65270dfb0579cd46..da9aa596b17811f7a282e86edf0c68de83229681 100644 (file)
--- a/xen/arch/x86/msr.c
+++ b/xen/arch/x86/msr.c
@@ -247,7 +247,7 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val)
             goto gp_fault; /* Rsvd bit set? */
 
         if ( v == curr )
-            wrmsrl(MSR_PRED_CMD, PRED_CMD_IBPB);
+            wrmsrl(MSR_PRED_CMD, val);
         break;
 
     case MSR_INTEL_MISC_FEATURES_ENABLES: