jz .L_stack_set
/* APs only: get stack base from APIC ID saved in %esp. */
- mov $0, %rax
+ mov $0, %rbx
lea cpu_data(%rip), %rcx
/* cpu_data[0] is BSP, skip it. */
1:
- add $1, %rax
+ add $1, %rbx
add $CPUINFO_X86_sizeof, %rcx
- cmp $NR_CPUS, %eax
+ cmp $NR_CPUS, %rbx
jb 2f
hlt
2:
cmp %esp, CPUINFO_X86_apicid(%rcx)
jne 1b
- /* %rcx is now cpu_data[cpu], read stack base from it. */
+ /*
+ * At this point:
+ * - %rcx is cpu_data[cpu], read stack base from it,
+ * - %rbx (callee-save) is Xen cpu number, pass it to start_secondary().
+ */
mov CPUINFO_X86_stack_base(%rcx), %rsp
test %rsp,%rsp
.L_ap_cet_done:
#endif /* CONFIG_XEN_SHSTK || CONFIG_XEN_IBT */
+ mov %rbx, %rdi
call start_secondary
BUG /* start_secondary() shouldn't return. */
cpu_relax();
}
-static int booting_cpu;
-
/* CPUs for which sibling maps can be computed. */
static cpumask_t cpu_sibling_setup_map;
}
}
-void start_secondary(void *unused)
+void start_secondary(unsigned int cpu)
{
struct cpu_info *info = get_cpu_info();
/*
- * Dont put anything before smp_callin(), SMP booting is so fragile that we
+ * Don't put anything before smp_callin(), SMP booting is so fragile that we
* want to limit the things done here to the most necessary things.
*/
- unsigned int cpu = booting_cpu;
if ( slaunch_active ) {
uint64_t misc_enable;
asm volatile ("monitor; xor %0,%0; mwait"
:: "a"(__va(sinit_mle->rlp_wakeup_addr)), "c"(0),
"d"(0) : "memory");
- cpu = booting_cpu;
}
}
*/
spin_debug_disable();
- get_cpu_info()->use_pv_cr3 = false;
- get_cpu_info()->xen_cr3 = 0;
- get_cpu_info()->pv_cr3 = 0;
+ info->use_pv_cr3 = false;
+ info->xen_cr3 = 0;
+ info->pv_cr3 = 0;
/*
* BUG_ON() used in load_system_tables() and later code may end up calling
*/
mtrr_save_state();
- booting_cpu = cpu;
-
start_eip = bootsym_phys(trampoline_realmode_entry);
/* start_eip needs be page aligned, and below the 1M boundary. */