#include <asm/apic.h>
#include <asm/hvm/support.h>
+#include <asm/hvm/vlapic.h>
#include "private.h"
uint8_t ReservedZBytePadding[PAGE_SIZE];
} HV_VP_ASSIST_PAGE;
+typedef enum HV_MESSAGE_TYPE {
+ HvMessageTypeNone,
+ HvMessageTimerExpired = 0x80000010,
+} HV_MESSAGE_TYPE;
+
+typedef struct HV_MESSAGE_FLAGS {
+ uint8_t MessagePending:1;
+ uint8_t Reserved:7;
+} HV_MESSAGE_FLAGS;
+
+typedef struct HV_MESSAGE_HEADER {
+ HV_MESSAGE_TYPE MessageType;
+ uint16_t Reserved1;
+ HV_MESSAGE_FLAGS MessageFlags;
+ uint8_t PayloadSize;
+ uint64_t Reserved2;
+} HV_MESSAGE_HEADER;
+
+#define HV_MESSAGE_SIZE 256
+#define HV_MESSAGE_MAX_PAYLOAD_QWORD_COUNT 30
+
+typedef struct HV_MESSAGE {
+ HV_MESSAGE_HEADER Header;
+ uint64_t Payload[HV_MESSAGE_MAX_PAYLOAD_QWORD_COUNT];
+} HV_MESSAGE;
+
+void __init __maybe_unused build_assertions(void)
+{
+ BUILD_BUG_ON(sizeof(HV_MESSAGE) != HV_MESSAGE_SIZE);
+}
+
void viridian_apic_assist_set(const struct vcpu *v)
{
struct viridian_vcpu *vv = v->arch.hvm.viridian;
struct viridian_vcpu *vv = v->arch.hvm.viridian;
struct domain *d = v->domain;
+ ASSERT(v == current || !v->is_running);
+
switch ( idx )
{
case HV_X64_MSR_EOI:
viridian_map_guest_page(d, &vv->vp_assist);
break;
+ case HV_X64_MSR_SCONTROL:
+ if ( !(viridian_feature_mask(d) & HVMPV_synic) )
+ return X86EMUL_EXCEPTION;
+
+ vv->scontrol = val;
+ break;
+
+ case HV_X64_MSR_SVERSION:
+ return X86EMUL_EXCEPTION;
+
+ case HV_X64_MSR_SIEFP:
+ if ( !(viridian_feature_mask(d) & HVMPV_synic) )
+ return X86EMUL_EXCEPTION;
+
+ vv->siefp = val;
+ break;
+
+ case HV_X64_MSR_SIMP:
+ if ( !(viridian_feature_mask(d) & HVMPV_synic) )
+ return X86EMUL_EXCEPTION;
+
+ viridian_unmap_guest_page(&vv->simp);
+ vv->simp.msr.raw = val;
+ viridian_dump_guest_page(v, "SIMP", &vv->simp);
+ if ( vv->simp.msr.enabled )
+ viridian_map_guest_page(d, &vv->simp);
+ break;
+
+ case HV_X64_MSR_EOM:
+ if ( !(viridian_feature_mask(d) & HVMPV_synic) )
+ return X86EMUL_EXCEPTION;
+
+ vv->msg_pending = 0;
+ break;
+
+ case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
+ {
+ unsigned int sintx = idx - HV_X64_MSR_SINT0;
+ union viridian_sint_msr new, *vs =
+ &array_access_nospec(vv->sint, sintx);
+ uint8_t vector;
+
+ if ( !(viridian_feature_mask(d) & HVMPV_synic) )
+ return X86EMUL_EXCEPTION;
+
+ /* Vectors must be in the range 0x10-0xff inclusive */
+ new.raw = val;
+ if ( new.vector < 0x10 )
+ return X86EMUL_EXCEPTION;
+
+ /*
+ * Invalidate any previous mapping by setting an out-of-range
+ * index before setting the new mapping.
+ */
+ vector = vs->vector;
+ vv->vector_to_sintx[vector] = ARRAY_SIZE(vv->sint);
+
+ vector = new.vector;
+ vv->vector_to_sintx[vector] = sintx;
+
+ printk(XENLOG_G_INFO "%pv: VIRIDIAN SINT%u: vector: %x\n", v, sintx,
+ vector);
+
+ if ( new.polling )
+ __clear_bit(sintx, &vv->msg_pending);
+
+ *vs = new;
+ break;
+ }
+
default:
gdprintk(XENLOG_INFO, "%s: unimplemented MSR %#x (%016"PRIx64")\n",
__func__, idx, val);
int viridian_synic_rdmsr(const struct vcpu *v, uint32_t idx, uint64_t *val)
{
+ const struct viridian_vcpu *vv = v->arch.hvm.viridian;
+ const struct domain *d = v->domain;
+
switch ( idx )
{
case HV_X64_MSR_EOI:
*val = ((uint64_t)icr2 << 32) | icr;
break;
}
+
case HV_X64_MSR_TPR:
*val = vlapic_get_reg(vcpu_vlapic(v), APIC_TASKPRI);
break;
case HV_X64_MSR_VP_ASSIST_PAGE:
- *val = v->arch.hvm.viridian->vp_assist.msr.raw;
+ *val = vv->vp_assist.msr.raw;
+ break;
+
+ case HV_X64_MSR_SCONTROL:
+ if ( !(viridian_feature_mask(d) & HVMPV_synic) )
+ return X86EMUL_EXCEPTION;
+
+ *val = vv->scontrol;
+ break;
+
+ case HV_X64_MSR_SVERSION:
+ if ( !(viridian_feature_mask(d) & HVMPV_synic) )
+ return X86EMUL_EXCEPTION;
+
+ /*
+ * The specification says that the version number is 0x00000001
+ * and should be in the lower 32-bits of the MSR, while the
+ * upper 32-bits are reserved... but it doesn't say what they
+ * should be set to. Assume everything but the bottom bit
+ * should be zero.
+ */
+ *val = 1ul;
+ break;
+
+ case HV_X64_MSR_SIEFP:
+ if ( !(viridian_feature_mask(d) & HVMPV_synic) )
+ return X86EMUL_EXCEPTION;
+
+ *val = vv->siefp;
+ break;
+
+ case HV_X64_MSR_SIMP:
+ if ( !(viridian_feature_mask(d) & HVMPV_synic) )
+ return X86EMUL_EXCEPTION;
+
+ *val = vv->simp.msr.raw;
break;
+ case HV_X64_MSR_EOM:
+ if ( !(viridian_feature_mask(d) & HVMPV_synic) )
+ return X86EMUL_EXCEPTION;
+
+ *val = 0;
+ break;
+
+ case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
+ {
+ unsigned int sintx = idx - HV_X64_MSR_SINT0;
+ const union viridian_sint_msr *vs =
+ &array_access_nospec(vv->sint, sintx);
+
+ if ( !(viridian_feature_mask(d) & HVMPV_synic) )
+ return X86EMUL_EXCEPTION;
+
+ *val = vs->raw;
+ break;
+ }
+
default:
gdprintk(XENLOG_INFO, "%s: unimplemented MSR %#x\n", __func__, idx);
return X86EMUL_EXCEPTION;
int viridian_synic_vcpu_init(const struct vcpu *v)
{
+ struct viridian_vcpu *vv = v->arch.hvm.viridian;
+ unsigned int i;
+
+ /*
+ * The specification says that all synthetic interrupts must be
+ * initally masked.
+ */
+ for ( i = 0; i < ARRAY_SIZE(vv->sint); i++ )
+ vv->sint[i].mask = 1;
+
+ /* Initialize the mapping array with invalid values */
+ for ( i = 0; i < ARRAY_SIZE(vv->vector_to_sintx); i++ )
+ vv->vector_to_sintx[i] = ARRAY_SIZE(vv->sint);
+
return 0;
}
void viridian_synic_vcpu_deinit(const struct vcpu *v)
{
- viridian_unmap_guest_page(&v->arch.hvm.viridian->vp_assist);
+ struct viridian_vcpu *vv = v->arch.hvm.viridian;
+
+ viridian_unmap_guest_page(&vv->vp_assist);
+ viridian_unmap_guest_page(&vv->simp);
}
void viridian_synic_domain_deinit(const struct domain *d)
{
}
+void viridian_synic_poll(const struct vcpu *v)
+{
+ /* There are currently no message sources */
+}
+
+bool viridian_synic_is_auto_eoi_sint(const struct vcpu *v,
+ unsigned int vector)
+{
+ const struct viridian_vcpu *vv = v->arch.hvm.viridian;
+ unsigned int sintx = vv->vector_to_sintx[vector];
+ const union viridian_sint_msr *vs =
+ &array_access_nospec(vv->sint, sintx);
+
+ if ( sintx >= ARRAY_SIZE(vv->sint) )
+ return false;
+
+ return vs->auto_eoi;
+}
+
+void viridian_synic_ack_sint(const struct vcpu *v, unsigned int vector)
+{
+ struct viridian_vcpu *vv = v->arch.hvm.viridian;
+ unsigned int sintx = vv->vector_to_sintx[vector];
+
+ ASSERT(v == current);
+
+ if ( sintx < ARRAY_SIZE(vv->sint) )
+ __clear_bit(array_index_nospec(sintx, ARRAY_SIZE(vv->sint)),
+ &vv->msg_pending);
+}
+
void viridian_synic_save_vcpu_ctxt(const struct vcpu *v,
struct hvm_viridian_vcpu_context *ctxt)
{
const struct viridian_vcpu *vv = v->arch.hvm.viridian;
+ unsigned int i;
+
+ BUILD_BUG_ON(ARRAY_SIZE(vv->sint) != ARRAY_SIZE(ctxt->sint_msr));
+
+ for ( i = 0; i < ARRAY_SIZE(vv->sint); i++ )
+ ctxt->sint_msr[i] = vv->sint[i].raw;
+
+ ctxt->simp_msr = vv->simp.msr.raw;
ctxt->apic_assist_pending = vv->apic_assist_pending;
ctxt->vp_assist_msr = vv->vp_assist.msr.raw;
{
struct viridian_vcpu *vv = v->arch.hvm.viridian;
struct domain *d = v->domain;
+ unsigned int i;
vv->vp_assist.msr.raw = ctxt->vp_assist_msr;
if ( vv->vp_assist.msr.enabled )
viridian_map_guest_page(d, &vv->vp_assist);
vv->apic_assist_pending = ctxt->apic_assist_pending;
+
+ vv->simp.msr.raw = ctxt->simp_msr;
+ if ( vv->simp.msr.enabled )
+ viridian_map_guest_page(d, &vv->simp);
+
+ for ( i = 0; i < ARRAY_SIZE(vv->sint); i++ )
+ {
+ uint8_t vector;
+
+ vv->sint[i].raw = ctxt->sint_msr[i];
+
+ vector = vv->sint[i].vector;
+ if ( vector < 0x10 )
+ continue;
+
+ vv->vector_to_sintx[vector] = i;
+ }
}
void viridian_synic_save_domain_ctxt(
/* Viridian CPUID leaf 3, Hypervisor Feature Indication */
#define CPUID3D_CRASH_MSRS (1 << 10)
+#define CPUID3D_SINT_POLLING (1 << 17)
/* Viridian CPUID leaf 4: Implementation Recommendations. */
#define CPUID4A_HCALL_REMOTE_TLB_FLUSH (1 << 2)
mask.AccessPartitionReferenceCounter = 1;
if ( viridian_feature_mask(d) & HVMPV_reference_tsc )
mask.AccessPartitionReferenceTsc = 1;
+ if ( viridian_feature_mask(d) & HVMPV_synic )
+ mask.AccessSynicRegs = 1;
u.mask = mask;
if ( viridian_feature_mask(d) & HVMPV_crash_ctl )
res->d = CPUID3D_CRASH_MSRS;
+ if ( viridian_feature_mask(d) & HVMPV_synic )
+ res->d |= CPUID3D_SINT_POLLING;
break;
}
case HV_X64_MSR_ICR:
case HV_X64_MSR_TPR:
case HV_X64_MSR_VP_ASSIST_PAGE:
+ case HV_X64_MSR_SCONTROL:
+ case HV_X64_MSR_SVERSION:
+ case HV_X64_MSR_SIEFP:
+ case HV_X64_MSR_SIMP:
+ case HV_X64_MSR_EOM:
+ case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
return viridian_synic_wrmsr(v, idx, val);
+ case HV_X64_MSR_TSC_FREQUENCY:
+ case HV_X64_MSR_APIC_FREQUENCY:
case HV_X64_MSR_REFERENCE_TSC:
return viridian_time_wrmsr(v, idx, val);
case HV_X64_MSR_ICR:
case HV_X64_MSR_TPR:
case HV_X64_MSR_VP_ASSIST_PAGE:
+ case HV_X64_MSR_SCONTROL:
+ case HV_X64_MSR_SVERSION:
+ case HV_X64_MSR_SIEFP:
+ case HV_X64_MSR_SIMP:
+ case HV_X64_MSR_EOM:
+ case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
return viridian_synic_rdmsr(v, idx, val);
case HV_X64_MSR_TSC_FREQUENCY:
projects / people / sstabellini / xen-unstable.git / .git / commitdiff