HACK! arm: set v7 translation table entries as uncachable

There appears to be a bug in the model where the MMU does not
correctly see updates to translation table entries if they are marked
as cachable.  This bug only happens when running under the Xen
hypervisor.

As a workaround, mark the entries as uncachable.  This decreases
performance.

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 2c559ac381425d325757c68d83e73c37c77e6b5d..4f56b3ffe88b230ff5e5678d9925ea8e14f7be43 100644 (file)
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -31,11 +31,11 @@
 #define TTB_IRGN_WB    ((1 << 0) | (1 << 6))
 
 /* PTWs cacheable, inner WB not shareable, outer WB not shareable */
-#define TTB_FLAGS_UP   TTB_IRGN_WB|TTB_RGN_OC_WB
+#define TTB_FLAGS_UP   TTB_IRGN_NC|TTB_RGN_NC
 #define PMD_FLAGS_UP   PMD_SECT_WB
 
 /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
-#define TTB_FLAGS_SMP  TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
+#define TTB_FLAGS_SMP  TTB_IRGN_NC|TTB_S|TTB_NOS|TTB_RGN_NC
 #define PMD_FLAGS_SMP  PMD_SECT_WBWA|PMD_SECT_S
 
 ENTRY(cpu_v7_proc_init)