u32 baseaddr = pci_config_readl(bdf, PCI_BASE_ADDRESS_0);
struct ehci_caps *caps = (void*)(baseaddr & PCI_BASE_ADDRESS_MEM_MASK);
u32 hcc_params = readl(&caps->hccparams);
- if (hcc_params & HCC_64BIT_ADDR) {
- dprintf(1, "No support for 64bit EHCI\n");
- return -1;
- }
struct usb_ehci_s *cntl = malloc_tmphigh(sizeof(*cntl));
if (!cntl) {
cntl->usb.pci = pci;
cntl->usb.type = USB_TYPE_EHCI;
cntl->caps = caps;
+ if (hcc_params & HCC_64BIT_ADDR)
+ cntl->regs->ctrldssegment = 0;
cntl->regs = (void*)caps + readb(&caps->caplength);
dprintf(1, "EHCI init on dev %02x:%02x.%x (regs=%p)\n"
#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
-#define EHCI_QH_ALIGN 64 // Can't span a 4K boundary, so increase to 64
+#define EHCI_QH_ALIGN 128 // Can't span a 4K boundary, so increase from 32
struct ehci_qh {
u32 next;
u32 alt_next;
u32 token;
u32 buf[5];
- // u32 buf_hi[5];
+ u32 buf_hi[5];
} PACKED;
#define QH_CONTROL (1 << 27)
#define EHCI_PTR_QH 0x0002
-#define EHCI_QTD_ALIGN 32
+#define EHCI_QTD_ALIGN 64 // Can't span a 4K boundary, so increase from 32
struct ehci_qtd {
u32 qtd_next;
u32 alt_next;
u32 token;
u32 buf[5];
- //u32 buf_hi[5];
-} PACKED;
+ u32 buf_hi[5];
+ /* keep struct size a multiple of 64 bytes, as we're allocating
+ arrays. Without this padding, the second qtd could have the
+ wrong alignment. */
+} PACKED __aligned(EHCI_QTD_ALIGN);
#define QTD_TOGGLE (1 << 31)
#define QTD_LENGTH_SHIFT 16