Use the new acpi_pm_base variable instead.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
fadt->smi_cmd = cpu_to_le32(PORT_SMI_CMD);
fadt->acpi_enable = PIIX4_ACPI_ENABLE;
fadt->acpi_disable = PIIX4_ACPI_DISABLE;
- fadt->pm1a_evt_blk = cpu_to_le32(PORT_ACPI_PM_BASE);
- fadt->pm1a_cnt_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x04);
- fadt->pm_tmr_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x08);
+ fadt->pm1a_evt_blk = cpu_to_le32(acpi_pm_base);
+ fadt->pm1a_cnt_blk = cpu_to_le32(acpi_pm_base + 0x04);
+ fadt->pm_tmr_blk = cpu_to_le32(acpi_pm_base + 0x08);
fadt->gpe0_blk = cpu_to_le32(PIIX4_GPE0_BLK);
fadt->pm1_evt_len = 4;
fadt->pm1_cnt_len = 2;
fadt->smi_cmd = cpu_to_le32(PORT_SMI_CMD);
fadt->acpi_enable = ICH9_ACPI_ENABLE;
fadt->acpi_disable = ICH9_ACPI_DISABLE;
- fadt->pm1a_evt_blk = cpu_to_le32(PORT_ACPI_PM_BASE);
- fadt->pm1a_cnt_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x04);
- fadt->pm_tmr_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x08);
- fadt->gpe0_blk = cpu_to_le32(PORT_ACPI_PM_BASE + ICH9_PMIO_GPE0_STS);
+ fadt->pm1a_evt_blk = cpu_to_le32(acpi_pm_base);
+ fadt->pm1a_cnt_blk = cpu_to_le32(acpi_pm_base + 0x04);
+ fadt->pm_tmr_blk = cpu_to_le32(acpi_pm_base + 0x08);
+ fadt->gpe0_blk = cpu_to_le32(acpi_pm_base + ICH9_PMIO_GPE0_STS);
fadt->pm1_evt_len = 4;
fadt->pm1_cnt_len = 2;
fadt->pm_tmr_len = 4;
static struct acpi_20_generic_address acpi_reset_reg;
static u8 acpi_reset_val;
u32 acpi_pm1a_cnt VARFSEG;
+u16 acpi_pm_base = 0xb000;
#define acpi_ga_to_bdf(addr) pci_to_bdf(0, (addr >> 32) & 0xffff, (addr >> 16) & 0xffff)
#define PORT_SMI_STATUS 0x00b3
#define PORT_QEMU_CFG_CTL 0x0510
#define PORT_QEMU_CFG_DATA 0x0511
-#define PORT_ACPI_PM_BASE 0xb000
-#define PORT_SMB_BASE 0xb100
void qemu_preinit(void);
void qemu_platform_setup(void);
/* pm io base */
pci_config_writel(bdf, ICH9_LPC_PMBASE,
- PORT_ACPI_PM_BASE | ICH9_LPC_PMBASE_RTE);
+ acpi_pm_base | ICH9_LPC_PMBASE_RTE);
/* acpi enable, SCI: IRQ9 000b = irq9*/
pci_config_writeb(bdf, ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_ACPI_EN);
- acpi_pm1a_cnt = PORT_ACPI_PM_BASE + 0x04;
- pmtimer_setup(PORT_ACPI_PM_BASE + 0x08);
+ acpi_pm1a_cnt = acpi_pm_base + 0x04;
+ pmtimer_setup(acpi_pm_base + 0x08);
}
static void storage_ide_setup(struct pci_device *pci, void *arg)
// acpi sci is hardwired to 9
pci_config_writeb(bdf, PCI_INTERRUPT_LINE, 9);
- pci_config_writel(bdf, 0x40, PORT_ACPI_PM_BASE | 1);
+ pci_config_writel(bdf, 0x40, acpi_pm_base | 1);
pci_config_writeb(bdf, 0x80, 0x01); /* enable PM io space */
- pci_config_writel(bdf, 0x90, PORT_SMB_BASE | 1);
+ pci_config_writel(bdf, 0x90, (acpi_pm_base + 0x100) | 1);
pci_config_writeb(bdf, 0xd2, 0x09); /* enable SMBus io space */
}
PiixPmBDF = pci->bdf;
piix4_pm_config_setup(pci->bdf);
- acpi_pm1a_cnt = PORT_ACPI_PM_BASE + 0x04;
- pmtimer_setup(PORT_ACPI_PM_BASE + 0x08);
+ acpi_pm1a_cnt = acpi_pm_base + 0x04;
+ pmtimer_setup(acpi_pm_base + 0x08);
}
/* ICH9 SMBUS */
u16 bdf = dev->bdf;
/* map smbus into io space */
pci_config_writel(bdf, ICH9_SMB_SMB_BASE,
- PORT_SMB_BASE | PCI_BASE_ADDRESS_SPACE_IO);
+ (acpi_pm_base + 0x100) | PCI_BASE_ADDRESS_SPACE_IO);
/* enable SMBus */
pci_config_writeb(bdf, ICH9_SMB_HOSTC, ICH9_SMB_HOSTC_HST_EN);
void ich9_lpc_apmc_smm_setup(int isabdf, int mch_bdf)
{
/* check if SMM init is already done */
- u32 value = inl(PORT_ACPI_PM_BASE + ICH9_PMIO_SMI_EN);
+ u32 value = inl(acpi_pm_base + ICH9_PMIO_SMI_EN);
if (value & ICH9_PMIO_SMI_EN_APMC_EN)
return;
/* enable SMI generation when writing to the APMC register */
outl(value | ICH9_PMIO_SMI_EN_APMC_EN,
- PORT_ACPI_PM_BASE + ICH9_PMIO_SMI_EN);
+ acpi_pm_base + ICH9_PMIO_SMI_EN);
smm_relocate_and_restore();
void copy_acpi_rsdp(void *pos);
extern struct rsdp_descriptor *RsdpAddr;
extern u32 acpi_pm1a_cnt;
+extern u16 acpi_pm_base;
void *find_acpi_rsdp(void);
u32 find_resume_vector(void);
void acpi_reboot(void);