x86 architectural MSR/CR constants and instruction wrappers

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>

diff --git a/include/arch/x86/lib.h b/include/arch/x86/lib.h
new file mode 100644 (file)
index 0000000..e8faa95
--- /dev/null
+++ b/include/arch/x86/lib.h
@@ -0,0 +1,92 @@
+#ifndef XTF_X86_LIB_H
+#define XTF_X86_LIB_H
+
+#include <stdint.h>
+
+static inline uint64_t rdmsr(uint32_t idx)
+{
+    uint32_t lo, hi;
+
+    asm volatile("rdmsr": "=a" (lo), "=d" (hi): "c" (idx));
+
+    return (((uint64_t)hi) << 32) | lo;
+}
+
+static inline void wrmsr(uint32_t idx, uint64_t val)
+{
+    asm volatile ("wrmsr":
+                  : "c" (idx), "a" ((uint32_t)val),
+                    "d" ((uint32_t)(val >> 32)));
+}
+
+static inline void cpuid(uint32_t leaf,
+                         uint32_t *eax, uint32_t *ebx,
+                         uint32_t *ecx, uint32_t *edx)
+{
+    asm volatile ("cpuid"
+                  : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx)
+                  : "0" (leaf));
+}
+
+static inline void cpuid_count(uint32_t leaf, uint32_t subleaf,
+                               uint32_t *eax, uint32_t *ebx,
+                               uint32_t *ecx, uint32_t *edx)
+{
+    asm volatile ("cpuid"
+                  : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx)
+                  : "0" (leaf), "2" (subleaf));
+}
+
+static inline uint8_t inb(uint16_t port)
+{
+    uint8_t val;
+
+    asm volatile("inb %w1, %b0": "=a" (val): "Nd" (port));
+
+    return val;
+}
+
+static inline uint16_t inw(uint16_t port)
+{
+    uint16_t val;
+
+    asm volatile("inw %w1, %w0": "=a" (val): "Nd" (port));
+
+    return val;
+}
+
+static inline uint32_t inl(uint16_t port)
+{
+    uint32_t val;
+
+    asm volatile("inl %w1, %k0": "=a" (val): "Nd" (port));
+
+    return val;
+}
+
+static inline void outb(uint8_t val, uint16_t port)
+{
+    asm volatile("outb %b0, %w1": : "a" (val), "Nd" (port));
+}
+
+static inline void outw(uint16_t val, uint16_t port)
+{
+    asm volatile("outw %w0, %w1": : "a" (val), "Nd" (port));
+}
+
+static inline void outl(uint32_t val, uint16_t port)
+{
+    asm volatile("outl %k0, %w1": : "a" (val), "Nd" (port));
+}
+
+#endif /* XTF_X86_LIB_H */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * tab-width: 4
+ * indent-tabs-mode: nil
+ * End:
+ */

diff --git a/include/arch/x86/msr-index.h b/include/arch/x86/msr-index.h
new file mode 100644 (file)
index 0000000..92779c1
--- /dev/null
+++ b/include/arch/x86/msr-index.h
@@ -0,0 +1,19 @@
+#ifndef XFT_X86_MSR_INDEX_H
+#define XFT_X86_MSR_INDEX_H
+
+#define MSR_EFER                        0xc0000080 /* Extended Feature register */
+#define _EFER_LME                       8  /* Long mode enable */
+#define EFER_LME                        (1<<_EFER_LME)
+
+#endif /* XFT_X86_MSR_INDEX_H */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * tab-width: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
+

diff --git a/include/arch/x86/processor.h b/include/arch/x86/processor.h
new file mode 100644 (file)
index 0000000..3276b7d
--- /dev/null
+++ b/include/arch/x86/processor.h
@@ -0,0 +1,73 @@
+#ifndef XTF_X86_PROCESSOR_H
+#define XTF_X86_PROCESSOR_H
+
+/*
+ * EFLAGS bits.
+ */
+#define X86_EFLAGS_CF           0x00000001 /* Carry Flag                */
+#define X86_EFLAGS_MBS          0x00000002 /* Resvd bit                 */
+#define X86_EFLAGS_PF           0x00000004 /* Parity Flag               */
+#define X86_EFLAGS_AF           0x00000010 /* Auxillary carry Flag      */
+#define X86_EFLAGS_ZF           0x00000040 /* Zero Flag                 */
+#define X86_EFLAGS_SF           0x00000080 /* Sign Flag                 */
+#define X86_EFLAGS_TF           0x00000100 /* Trap Flag                 */
+#define X86_EFLAGS_IF           0x00000200 /* Interrupt Flag            */
+#define X86_EFLAGS_DF           0x00000400 /* Direction Flag            */
+#define X86_EFLAGS_OF           0x00000800 /* Overflow Flag             */
+#define X86_EFLAGS_IOPL         0x00003000 /* IOPL mask                 */
+#define X86_EFLAGS_NT           0x00004000 /* Nested Task               */
+#define X86_EFLAGS_RF           0x00010000 /* Resume Flag               */
+#define X86_EFLAGS_VM           0x00020000 /* Virtual Mode              */
+#define X86_EFLAGS_AC           0x00040000 /* Alignment Check           */
+#define X86_EFLAGS_VIF          0x00080000 /* Virtual Interrupt Flag    */
+#define X86_EFLAGS_VIP          0x00100000 /* Virtual Interrupt Pending */
+#define X86_EFLAGS_ID           0x00200000 /* CPUID detection flag      */
+
+/*
+ * CPU flags in CR0.
+ */
+#define X86_CR0_PE              0x00000001 /* Enable Protected Mode    (RW) */
+#define X86_CR0_MP              0x00000002 /* Monitor Coprocessor      (RW) */
+#define X86_CR0_EM              0x00000004 /* Require FPU Emulation    (RO) */
+#define X86_CR0_TS              0x00000008 /* Task Switched            (RW) */
+#define X86_CR0_ET              0x00000010 /* Extension type           (RO) */
+#define X86_CR0_NE              0x00000020 /* Numeric Error Reporting  (RW) */
+#define X86_CR0_WP              0x00010000 /* Supervisor Write Protect (RW) */
+#define X86_CR0_AM              0x00040000 /* Alignment Checking       (RW) */
+#define X86_CR0_NW              0x20000000 /* Not Write-Through        (RW) */
+#define X86_CR0_CD              0x40000000 /* Cache Disable            (RW) */
+#define X86_CR0_PG              0x80000000 /* Paging                   (RW) */
+
+/*
+ * CPU features in CR4.
+ */
+#define X86_CR4_VME             0x00000001  /* VM86 extensions                */
+#define X86_CR4_PVI             0x00000002  /* Virtual interrupts flag        */
+#define X86_CR4_TSD             0x00000004  /* Disable time stamp at ipl 3    */
+#define X86_CR4_DE              0x00000008  /* Debugging extensions           */
+#define X86_CR4_PSE             0x00000010  /* Page size extensions           */
+#define X86_CR4_PAE             0x00000020  /* Physical address extensions    */
+#define X86_CR4_MCE             0x00000040  /* Machine check                  */
+#define X86_CR4_PGE             0x00000080  /* Global pages                   */
+#define X86_CR4_PCE             0x00000100  /* Performance counters at ipl 3  */
+#define X86_CR4_OSFXSR          0x00000200  /* Fast FPU save and restore      */
+#define X86_CR4_OSXMMEXCPT      0x00000400  /* Unmasked SSE exceptions        */
+#define X86_CR4_VMXE            0x00002000  /* VMX                            */
+#define X86_CR4_SMXE            0x00004000  /* SMX                            */
+#define X86_CR4_FSGSBASE        0x00010000  /* {rd,wr}{fs,gs}base             */
+#define X86_CR4_PCIDE           0x00020000  /* PCID                           */
+#define X86_CR4_OSXSAVE         0x00040000  /* XSAVE/XRSTOR                   */
+#define X86_CR4_SMEP            0x00100000  /* SMEP                           */
+#define X86_CR4_SMAP            0x00200000  /* SMAP                           */
+
+#endif /* XTF_X86_PROCESSOR_H */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * tab-width: 4
+ * indent-tabs-mode: nil
+ * End:
+ */

diff --git a/include/xtf/lib.h b/include/xtf/lib.h
index 232f010dc6aaa36be6c65cdd7c2dbfbcc182de63..fa7d68479b57541a58480d79b47fa7ddd22753fe 100644 (file)
--- a/include/xtf/lib.h
+++ b/include/xtf/lib.h
@@ -4,6 +4,8 @@
 #include <xtf/types.h>
 #include <xtf/compiler.h>
 
+#include <arch/x86/lib.h>
+
 #define ARRAY_SIZE(a)    (sizeof(a) / sizeof(*a))
 
 #define ACCESS_ONCE(x)   (*(volatile typeof(x) *)&(x))