{
dprintf(3, "init ivt\n");
+ // Setup reset-vector entry point (controls legacy reboots).
+ HaveRunPost = 1;
+ outb_cmos(0, CMOS_RESET_CODE);
+
// Initialize all vectors to the default handler.
int i;
for (i=0; i<256; i++)
static void
platform_hardware_setup(void)
{
+ // Enable CPU caching
+ setcr0(getcr0() & ~(CR0_CD|CR0_NW));
+
+ // Make sure legacy DMA isn't running.
+ dma_setup();
+
// Init base pc hardware.
pic_setup();
timer_setup();
void VISIBLE32INIT
dopost(void)
{
- // Set reboot flags.
- HaveRunPost = 1;
- outb_cmos(0, CMOS_RESET_CODE);
-
- // Enable CPU caching
- setcr0(getcr0() & ~(CR0_CD|CR0_NW));
-
- // Make sure legacy DMA isn't running.
- dma_preinit();
-
// Check if we are running under Xen.
xen_preinit();
// Reset DMA controller
void
-dma_preinit(void)
+dma_setup(void)
{
// first reset the DMA controllers
outb(0, PORT_DMA1_MASTER_CLEAR);
outb_cmos(0, CMOS_RESET_CODE);
dprintf(1, "In resume (status=%d)\n", status);
- dma_preinit();
+ dma_setup();
switch (status) {
case 0x01 ... 0x04: