x86/Intel: Mitigations for GPZ SP4 - Speculative Store Bypass

To combat GPZ SP4 "Speculative Store Bypass", Intel have extended their
speculative sidechannel mitigations specification as follows:

 * A feature bit to indicate that Speculative Store Bypass Disable is
   supported.
 * A new bit in MSR_SPEC_CTRL which, when set, disables memory disambiguation
   in the pipeline.
 * A new bit in MSR_ARCH_CAPABILITIES, which will be set in future hardware,
   indicating that the hardware is not susceptible to Speculative Store Bypass
   sidechannels.

For contemporary processors, this interface will be implemented via a
microcode update.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>

diff --git a/docs/misc/xen-command-line.markdown b/docs/misc/xen-command-line.markdown
index da570b4ab1a82abd6df1a8a0c1b996e2ab24fd98..8712a833a29540aba337731c38f776152db3ed6c 100644 (file)
--- a/docs/misc/xen-command-line.markdown
+++ b/docs/misc/xen-command-line.markdown
@@ -489,9 +489,10 @@ accounting for hardware capabilities as enumerated via CPUID.
 
 Currently accepted:
 
-The Speculation Control hardware features `ibrsb`, `stibp`, `ibpb` are used by
-default if avaiable.  They can be ignored, e.g. `no-ibrsb`, at which point Xen
-won't use them itself, and won't offer them to guests.
+The Speculation Control hardware features `ibrsb`, `stibp`, `ibpb`, `ssbd` are
+used by default if available and applicable.  They can be ignored,
+e.g. `no-ibrsb`, at which point Xen won't use them itself, and won't offer
+them to guests.
 
 ### cpuid\_mask\_cpu (AMD only)
 > `= fam_0f_rev_c | fam_0f_rev_d | fam_0f_rev_e | fam_0f_rev_f | fam_0f_rev_g | fam_10_rev_b | fam_10_rev_c | fam_11_rev_b`
@@ -1782,7 +1783,7 @@ protect itself, and Xen's ability to virtualise support for guests to use.
   respectively.
 * `msr-sc=` offers control over Xen's support for manipulating MSR\_SPEC\_CTRL
   on entry and exit.  These blocks are necessary to virtualise support for
-  guests and if disabled, guests will be unable to use IBRS/STIBP/etc.
+  guests and if disabled, guests will be unable to use IBRS/STIBP/SSBD/etc.
 * `rsb=` offers control over whether to overwrite the Return Stack Buffer /
   Return Address Stack on entry to Xen.
 
@@ -1804,7 +1805,8 @@ prediction barriers on vcpu context switches.
 On hardware supporting SSBD (Speculative Store Bypass Disable), the `ssbd=`
 option can be used to force or prevent Xen using the feature itself.  On AMD
 hardware, this is a global option applied at boot, and not virtualised for
-guest use.
+guest use.  On Intel hardware, the feature is virtualised for guests,
+independently of Xen's choice of setting.
 
 ### sync\_console
 > `= <boolean>`

diff --git a/tools/libxl/libxl_cpuid.c b/tools/libxl/libxl_cpuid.c
index 3a21f4e7dad080b403dbccd6bc2ba3b5d237e5ff..7b0f594c3d5210686c45c6890d1c80bd3fd2b68d 100644 (file)
--- a/tools/libxl/libxl_cpuid.c
+++ b/tools/libxl/libxl_cpuid.c
@@ -205,6 +205,7 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str)
         {"ibrsb",        0x00000007,  0, CPUID_REG_EDX, 26,  1},
         {"stibp",        0x00000007,  0, CPUID_REG_EDX, 27,  1},
         {"arch-caps",    0x00000007,  0, CPUID_REG_EDX, 29,  1},
+        {"ssbd",         0x00000007,  0, CPUID_REG_EDX, 31,  1},
 
         {"lahfsahf",     0x80000001, NA, CPUID_REG_ECX,  0,  1},
         {"cmplegacy",    0x80000001, NA, CPUID_REG_ECX,  1,  1},

diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c
index adc7fcec74fb5347738588f4178a6eae3da3a463..e116339733b8dff20eda070cd3cec610fd03d870 100644 (file)
--- a/tools/misc/xen-cpuid.c
+++ b/tools/misc/xen-cpuid.c
@@ -144,6 +144,7 @@ static const char *str_7d0[32] =
 
     [26] = "ibrsb",         [27] = "stibp",
     /* 28 */                [29] = "arch_caps",
+    /* 30 */                [31] = "ssbd",
 };
 
 static struct {

diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c
index 827b6c56015b8fccc62192b6ae8414ab7f71cabf..4b8d33013f34c552c31627704dde43897460022c 100644 (file)
--- a/xen/arch/x86/cpuid.c
+++ b/xen/arch/x86/cpuid.c
@@ -43,6 +43,11 @@ static int __init parse_xen_cpuid(const char *s)
             if ( !val )
                 setup_clear_cpu_cap(X86_FEATURE_STIBP);
         }
+        else if ( (val = parse_boolean("ssbd", s, ss)) >= 0 )
+        {
+            if ( !val )
+                setup_clear_cpu_cap(X86_FEATURE_SSBD);
+        }
         else
             rc = -EINVAL;
 

diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c
index 20b215e31c113bfe18171afe040263e04de00465..2ccada2f6505b2bf0ea9937b9017b96799be7006 100644 (file)
--- a/xen/arch/x86/spec_ctrl.c
+++ b/xen/arch/x86/spec_ctrl.c
@@ -208,26 +208,31 @@ static void __init print_details(enum ind_thunk thunk, uint64_t caps)
     printk("Speculative mitigation facilities:\n");
 
     /* Hardware features which pertain to speculative mitigations. */
-    printk("  Hardware features:%s%s%s%s%s%s\n",
+    printk("  Hardware features:%s%s%s%s%s%s%s%s\n",
            (_7d0 & cpufeat_mask(X86_FEATURE_IBRSB)) ? " IBRS/IBPB" : "",
            (_7d0 & cpufeat_mask(X86_FEATURE_STIBP)) ? " STIBP"     : "",
+           (_7d0 & cpufeat_mask(X86_FEATURE_SSBD))  ? " SSBD"      : "",
            (e8b  & cpufeat_mask(X86_FEATURE_IBPB))  ? " IBPB"      : "",
            (caps & ARCH_CAPABILITIES_IBRS_ALL)      ? " IBRS_ALL"  : "",
            (caps & ARCH_CAPABILITIES_RDCL_NO)       ? " RDCL_NO"   : "",
-           (caps & ARCH_CAPS_RSBA)                  ? " RSBA"      : "");
+           (caps & ARCH_CAPS_RSBA)                  ? " RSBA"      : "",
+           (caps & ARCH_CAPS_SSBD_NO)               ? " SSBD_NO"   : "");
 
     /* Compiled-in support which pertains to BTI mitigations. */
     if ( IS_ENABLED(CONFIG_INDIRECT_THUNK) )
         printk("  Compiled-in support: INDIRECT_THUNK\n");
 
     /* Settings for Xen's protection, irrespective of guests. */
-    printk("  Xen settings: BTI-Thunk %s, SPEC_CTRL: %s, Other:%s\n",
+    printk("  Xen settings: BTI-Thunk %s, SPEC_CTRL: %s%s, Other:%s\n",
            thunk == THUNK_NONE      ? "N/A" :
            thunk == THUNK_RETPOLINE ? "RETPOLINE" :
            thunk == THUNK_LFENCE    ? "LFENCE" :
            thunk == THUNK_JMP       ? "JMP" : "?",
            !use_spec_ctrl                            ?  "No" :
            (default_xen_spec_ctrl & SPEC_CTRL_IBRS)  ?  "IBRS+" :  "IBRS-",
+           !use_spec_ctrl || !boot_cpu_has(X86_FEATURE_SSBD)
+                                                     ? "" :
+           (default_xen_spec_ctrl & SPEC_CTRL_SSBD)  ? " SSBD+" : " SSBD-",
            opt_ibpb                                  ? " IBPB"  : "");
 
     /*
@@ -496,6 +501,10 @@ void __init init_speculation_mitigations(void)
         }
     }
 
+    /* If we have SSBD available, see whether we should use it. */
+    if ( boot_cpu_has(X86_FEATURE_SSBD) && use_spec_ctrl && opt_ssbd )
+        default_xen_spec_ctrl |= SPEC_CTRL_SSBD;
+
     /*
      * PV guests can poison the RSB to any virtual address from which
      * they can execute a call instruction.  This is necessarily outside

diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index 6d94d655750308ca49e9bc3c54ecf167d9b257bb..0612a967491e90ba3616165cbce097e2a40f54ab 100644 (file)
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -38,6 +38,7 @@
 #define MSR_SPEC_CTRL                  0x00000048
 #define SPEC_CTRL_IBRS                 (_AC(1, ULL) << 0)
 #define SPEC_CTRL_STIBP                        (_AC(1, ULL) << 1)
+#define SPEC_CTRL_SSBD                 (_AC(1, ULL) << 2)
 
 #define MSR_PRED_CMD                   0x00000049
 #define PRED_CMD_IBPB                  (_AC(1, ULL) << 0)
@@ -46,6 +47,7 @@
 #define ARCH_CAPABILITIES_RDCL_NO      (_AC(1, ULL) << 0)
 #define ARCH_CAPABILITIES_IBRS_ALL     (_AC(1, ULL) << 1)
 #define ARCH_CAPS_RSBA                 (_AC(1, ULL) << 2)
+#define ARCH_CAPS_SSBD_NO              (_AC(1, ULL) << 4)
 
 /* Intel MSRs. Some also available on other CPUs */
 #define MSR_IA32_PERFCTR0              0x000000c1

diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h
index 8da5783f7aff0d07c353c1382a55699d78a20fc6..7acf8222accded535aab7c4ae5c06ba997adc4d4 100644 (file)
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -245,6 +245,7 @@ XEN_CPUFEATURE(AVX512_4FMAPS, 9*32+ 3) /*A  AVX512 Multiply Accumulation Single
 XEN_CPUFEATURE(IBRSB,         9*32+26) /*A  IBRS and IBPB support (used by Intel) */
 XEN_CPUFEATURE(STIBP,         9*32+27) /*A! STIBP */
 XEN_CPUFEATURE(ARCH_CAPS,     9*32+29) /*   IA32_ARCH_CAPABILITIES MSR */
+XEN_CPUFEATURE(SSBD,          9*32+31) /*   MSR_SPEC_CTRL.SSBD available */
 
 #endif /* XEN_CPUFEATURE */
 

diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py
index 6359afb70437b5ba7378ab0243381bb71ae09b0f..3fecae86d4aa3a788f662cf0c7e80ff351c6a185 100755 (executable)
--- a/xen/tools/gen-cpuid.py
+++ b/xen/tools/gen-cpuid.py
@@ -261,10 +261,19 @@ def crunch_numbers(state):
                   AVX512BW, AVX512VL, AVX512VBMI, AVX512_4VNNIW,
                   AVX512_4FMAPS, AVX512_VPOPCNTDQ],
 
-        # Single Thread Indirect Branch Predictors enumerates a new bit in the
-        # MSR enumerated by Indirect Branch Restricted Speculation/Indirect
-        # Branch Prediction Barrier enumeration.
-        IBRSB: [STIBP],
+        # The features:
+        #   * Single Thread Indirect Branch Predictors
+        #   * Speculative Store Bypass Disable
+        #
+        # enumerate new bits in MSR_SPEC_CTRL, which is enumerated by Indirect
+        # Branch Restricted Speculation/Indirect Branch Prediction Barrier.
+        #
+        # In practice, these features also enumerate the presense of
+        # MSR_SPEC_CTRL.  However, no real hardware will exist with SSBD but
+        # not IBRSB, and we pass this MSR directly to guests.  Treating them
+        # as dependent features simplifies Xen's logic, and prevents the guest
+        # from seeing implausible configurations.
+        IBRSB: [STIBP, SSBD],
     }
 
     deep_features = tuple(sorted(deps.keys()))