x86/spec-ctrl: Enable Zen2 chickenbit

... as instructed in the Branch Type Confusion whitepaper.

This is part of XSA-407.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>

diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index 618c7d5b2a4682007a9485456dd94468fc6e6146..29c59bcba4092ca94a3e3eb75a5930892c921652 100644 (file)
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -731,6 +731,31 @@ void amd_init_ssbd(const struct cpuinfo_x86 *c)
                printk_once(XENLOG_ERR "No SSBD controls available\n");
 }
 
+/*
+ * On Zen2 we offer this chicken (bit) on the altar of Speculation.
+ *
+ * Refer to the AMD Branch Type Confusion whitepaper:
+ * https://XXX
+ *
+ * Setting this unnamed bit supposedly causes prediction information on
+ * non-branch instructions to be ignored.  It is to be set unilaterally in
+ * newer microcode.
+ *
+ * This chickenbit is something unrelated on Zen1, and Zen1 vs Zen2 isn't a
+ * simple model number comparison, so use STIBP as a heuristic to separate the
+ * two uarches in Fam17h(AMD)/18h(Hygon).
+ */
+void amd_init_spectral_chicken(void)
+{
+       uint64_t val, chickenbit = 1 << 1;
+
+       if (cpu_has_hypervisor || !boot_cpu_has(X86_FEATURE_AMD_STIBP))
+               return;
+
+       if (rdmsr_safe(MSR_AMD64_DE_CFG2, val) == 0 && !(val & chickenbit))
+               wrmsr_safe(MSR_AMD64_DE_CFG2, val | chickenbit);
+}
+
 void __init detect_zen2_null_seg_behaviour(void)
 {
        uint64_t base;
@@ -796,6 +821,9 @@ static void cf_check init_amd(struct cpuinfo_x86 *c)
 
        amd_init_ssbd(c);
 
+       if (c->x86 == 0x17)
+               amd_init_spectral_chicken();
+
        /* Probe for NSCB on Zen2 CPUs when not virtualised */
        if (!cpu_has_hypervisor && !cpu_has_nscb && c == &boot_cpu_data &&
            c->x86 == 0x17)

diff --git a/xen/arch/x86/cpu/cpu.h b/xen/arch/x86/cpu/cpu.h
index a228087f91577ac597d6b353d42aa5f5e92ee5c5..85a67771f7b7d8b267e14dc62de1d6007efc1744 100644 (file)
--- a/xen/arch/x86/cpu/cpu.h
+++ b/xen/arch/x86/cpu/cpu.h
@@ -22,4 +22,5 @@ void cf_check early_init_amd(struct cpuinfo_x86 *c);
 void amd_log_freq(const struct cpuinfo_x86 *c);
 void amd_init_lfence(struct cpuinfo_x86 *c);
 void amd_init_ssbd(const struct cpuinfo_x86 *c);
+void amd_init_spectral_chicken(void);
 void detect_zen2_null_seg_behaviour(void);

diff --git a/xen/arch/x86/cpu/hygon.c b/xen/arch/x86/cpu/hygon.c
index 3c8516e014c3dbeb04e4abbd9e289573a28318fe..361eb6fd411b2a35a11aed7d4f44d93791b2a4fe 100644 (file)
--- a/xen/arch/x86/cpu/hygon.c
+++ b/xen/arch/x86/cpu/hygon.c
@@ -40,6 +40,12 @@ static void cf_check init_hygon(struct cpuinfo_x86 *c)
            c->x86 == 0x18)
                detect_zen2_null_seg_behaviour();
 
+       /*
+        * TODO: Check heuristic safety with Hygon first
+       if (c->x86 == 0x18)
+               amd_init_spectral_chicken();
+        */
+
        /*
         * Hygon CPUs before Zen2 don't clear segment bases/limits when
         * loading a NULL selector.

diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h
index bcb424a3202682ecbecbe65202551c3f42a65d57..8cab8736d8a5740251a7ce40856f5154cf069153 100644 (file)
--- a/xen/arch/x86/include/asm/msr-index.h
+++ b/xen/arch/x86/include/asm/msr-index.h
@@ -377,6 +377,7 @@
 #define MSR_AMD64_DE_CFG               0xc0011029
 #define AMD64_DE_CFG_LFENCE_SERIALISE  (_AC(1, ULL) << 1)
 #define MSR_AMD64_EX_CFG               0xc001102c
+#define MSR_AMD64_DE_CFG2              0xc00110e3
 
 #define MSR_AMD64_DR0_ADDRESS_MASK     0xc0011027
 #define MSR_AMD64_DR1_ADDRESS_MASK     0xc0011019