VMX: add new CPU families to LBR handling

Bring code up-to-date with SDM version 063, including the LBR format
enumeration.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>

diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index 43bc724da7dee52c5477bb9e935681d2ae680130..9cb6279aecc4eabedf3880982337a9b2e4ca33a2 100644 (file)
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -2726,6 +2726,8 @@ static const struct lbr_info *last_branch_msr_get(void)
         case 0x0f:
         /* Enhanced Core */
         case 0x17:
+        /* Xeon 7400 */
+        case 0x1d:
             return c2_lbr;
         /* Nehalem */
         case 0x1a: case 0x1e: case 0x1f: case 0x2e:
@@ -2742,6 +2744,12 @@ static const struct lbr_info *last_branch_msr_get(void)
             return nh_lbr;
         /* Skylake */
         case 0x4e: case 0x5e:
+        /* Xeon Scalable */
+        case 0x55:
+        /* Cannon Lake */
+        case 0x66:
+        /* Goldmont Plus */
+        case 0x7a:
         /* Kaby Lake */
         case 0x8e: case 0x9e:
             return sk_lbr;
@@ -2751,6 +2759,8 @@ static const struct lbr_info *last_branch_msr_get(void)
         case 0x37: case 0x4a: case 0x4d: case 0x5a: case 0x5d:
         /* Xeon Phi Knights Landing */
         case 0x57:
+        /* Xeon Phi Knights Mill */
+        case 0x85:
         /* Airmont */
         case 0x4c:
             return at_lbr;
@@ -2782,6 +2792,7 @@ enum
     LBR_FORMAT_EIP_FLAGS_TSX      = 0x4, /* 64-bit EIP, Flags, TSX */
     LBR_FORMAT_EIP_FLAGS_TSX_INFO = 0x5, /* 64-bit EIP, Flags, TSX, LBR_INFO */
     LBR_FORMAT_EIP_FLAGS_CYCLES   = 0x6, /* 64-bit EIP, Flags, Cycles */
+    LBR_FORMAT_LIP_FLAGS_TSX_INFO = 0x7, /* 64-bit LIP, Flags, TSX, LBR_INFO */
 };
 
 #define LBR_FROM_SIGNEXT_2MSB  ((1ULL << 59) | (1ULL << 60))