At the moment, the reset vector is defined as .word 0 (e.g andeq r0, r0,
r0).
This is rather unintuitive and will result to execute the trap
undefined. Instead introduce trap helpers for reset and will generate an
error message in the unlikely case that reset will be called.
This is part of XSA-254.
Signed-off-by: Julien Grall <julien.grall@linaro.org>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
(cherry picked from commit
00268cc91270c7b0aa3a1906bf7e7702db9c61c1)
Conflicts:
xen/arch/arm/arm32/traps.c
.align 5
GLOBAL(hyp_traps_vector)
- .word 0 /* 0x00 - Reset */
+ b trap_reset /* 0x00 - Reset */
b trap_undefined_instruction /* 0x04 - Undefined Instruction */
b trap_supervisor_call /* 0x08 - Supervisor Call */
b trap_prefetch_abort /* 0x0c - Prefetch Abort */
b trap_irq /* 0x18 - IRQ */
b trap_fiq /* 0x1c - FIQ */
+DEFINE_TRAP_ENTRY(reset)
DEFINE_TRAP_ENTRY(undefined_instruction)
DEFINE_TRAP_ENTRY(supervisor_call)
DEFINE_TRAP_ENTRY(prefetch_abort)
#include <asm/processor.h>
+asmlinkage void do_trap_reset(struct cpu_user_regs *regs)
+{
+ do_unexpected_trap("Reset", regs);
+}
+
asmlinkage void do_trap_undefined_instruction(struct cpu_user_regs *regs)
{
uint32_t pc = regs->pc;