if ( bar_sz == 0 )
continue;
+ if ( ((bar_data & PCI_BASE_ADDRESS_SPACE) ==
+ PCI_BASE_ADDRESS_SPACE_MEMORY) ||
+ (bar_reg == PCI_ROM_ADDRESS) )
+ /*
+ * Always roundup memory BAR sizes to the size of a page in
+ * order to prevent BARs being placed in the same page.
+ */
+ bar_sz = ROUNDUP(bar_sz, PAGE_SIZE);
+
for ( i = 0; i < nr_bars; i++ )
if ( bars[i].bar_sz < bar_sz )
break;
pci_writew(devfn, PCI_COMMAND, cmd);
}
+ ASSERT(IS_ALIGNED(mmio_total, PAGE_SIZE));
+
if ( mmio_hole_size )
{
uint64_t max_ram_below_4g = GB(4) - mmio_hole_size;
resource = &mem_resource;
bar_data &= ~PCI_BASE_ADDRESS_MEM_MASK;
}
+ ASSERT(bar_sz <= mmio_total);
mmio_total -= bar_sz;
}
else
#define MB(mb) (mb##ULL << 20)
#define GB(gb) (gb##ULL << 30)
+#define ROUNDUP(x, a) (((x) + (a) - 1) & ~((a) - 1))
+#define IS_ALIGNED(val, align) (((val) & ((align) - 1)) == 0)
+
static inline int test_bit(unsigned int b, const void *p)
{
return !!(((const uint8_t *)p)[b>>3] & (1u<<(b&7)));