x86/traps: Drop 32bit fields out of tss_struct

The backlink field doesn't exist in a 64bit TSS, and union for esp{0..2} is of
no practical use.  Specify everything with stdint types, and empty bitfields
for reserved values.

No functional change.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Wei Liu <wei.liu2@citrix.com>
Release-acked-by: Julien Grall <julien.grall@arm.com>

diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index ca0a04a6cb0c1f8ebd6eb0d793b9736fdd56c7d6..7fcdeeab26a46771edc089b9cb9596e80bf429d8 100644 (file)
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -459,9 +459,9 @@ void show_stack_overflow(unsigned int cpu, const struct cpu_user_regs *regs)
     esp_bottom = (esp | (STACK_SIZE - 1)) + 1;
     esp_top    = esp_bottom - PRIMARY_STACK_SIZE;
 
-    printk("Valid stack range: %p-%p, sp=%p, tss.esp0=%p\n",
+    printk("Valid stack range: %p-%p, sp=%p, tss.rsp0=%p\n",
            (void *)esp_top, (void *)esp_bottom, (void *)esp,
-           (void *)per_cpu(init_tss, cpu).esp0);
+           (void *)per_cpu(init_tss, cpu).rsp0);
 
     /*
      * Trigger overflow trace if %esp is anywhere within the guard page, or

diff --git a/xen/include/asm-x86/processor.h b/xen/include/asm-x86/processor.h
index 73dd3abd03af840a7975a85ea892501d2df39dcd..f244e105cd4105e34795f8742a6e5120f5a9dab7 100644 (file)
--- a/xen/include/asm-x86/processor.h
+++ b/xen/include/asm-x86/processor.h
@@ -428,19 +428,18 @@ static always_inline void __mwait(unsigned long eax, unsigned long ecx)
 #define IOBMP_INVALID_OFFSET    0x8000
 
 struct __packed __cacheline_aligned tss_struct {
-    unsigned short     back_link,__blh;
-    union { u64 rsp0, esp0; };
-    union { u64 rsp1, esp1; };
-    union { u64 rsp2, esp2; };
-    u64 reserved1;
-    u64 ist[7]; /* Interrupt Stack Table is 1-based so tss->ist[0]
-                 * corresponds to an IST value of 1 in an Interrupt
-                 * Descriptor */
-    u64 reserved2;
-    u16 reserved3;
-    u16 bitmap;
+    uint32_t :32;
+    uint64_t rsp0, rsp1, rsp2;
+    uint64_t :64;
+    /*
+     * Interrupt Stack Table is 1-based so tss->ist[0] corresponds to an IST
+     * value of 1 in an Interrupt Descriptor.
+     */
+    uint64_t ist[7];
+    uint64_t :64;
+    uint16_t :16, bitmap;
     /* Pads the TSS to be cacheline-aligned (total size is 0x80). */
-    u8 __cacheline_filler[24];
+    uint8_t __cacheline_filler[24];
 };
 
 #define IST_NONE 0UL