#define REG_SHIFT 2
+/* Register offsets */
+#define UART_OMAP_EFR 0x02 /* Enhanced feature register */
+#define UART_OMAP_MDR1 0x08 /* Mode definition register 1 */
+#define UART_OMAP_SCR 0x10 /* Supplementary control register */
+#define UART_OMAP_SYSC 0x15 /* System configuration register */
+
+/* Enhanced feature register */
+#define UART_OMAP_EFR_ECB 0x10 /* Enhanced control bit */
+
+/* Mode definition register 1 */
+#define UART_OMAP_MDR1_16X_MODE 0x00 /* UART 16x mode */
+#define UART_OMAP_MDR1_DISABLE 0x07 /* Disable (default state) */
+
+/* Supplementary control register bitmasks */
+#define UART_OMAP_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
+
+/* System configuration register */
+#define UART_OMAP_SYSC_DEF_CONF 0x0d /* autoidle mode, wakeup is enabled */
+
#define omap_read(uart, off) readl((uart)->regs + (off<<REG_SHIFT))
#define omap_write(uart, off, val) writel((val), (uart)->regs + (off<<REG_SHIFT))
/*
* Load the new FIFO triggers and the new DMA mode bit.
*/
- omap_write(uart, UART_OMAP_SCR, OMAP_UART_SCR_RX_TRIG_GRANU1_MASK);
+ omap_write(uart, UART_OMAP_SCR, UART_OMAP_SCR_RX_TRIG_GRANU1_MASK);
/*
* Restore the UART_OMAP_EFR[4] value.
*/
omap_write(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE);
- /* setup iddle mode */
- omap_write(uart, UART_SYSC, OMAP_UART_SYSC_DEF_CONF);
+ /* setup idle mode */
+ omap_write(uart, UART_OMAP_SYSC, UART_OMAP_SYSC_DEF_CONF);
}
static void __init omap_uart_init_postirq(struct serial_port *port)
#define UART_MCR 0x04 /* Modem control */
#define UART_LSR 0x05 /* line status */
#define UART_MSR 0x06 /* Modem status */
-#define UART_SYSC 0x15 /* System configuration register */
#define UART_USR 0x1f /* Status register (DW) */
#define UART_DLL 0x00 /* divisor latch (ls) (DLAB=1) */
#define UART_DLM 0x01 /* divisor latch (ms) (DLAB=1) */
#define RESUME_DELAY MILLISECS(10)
#define RESUME_RETRIES 100
-/* Enhanced feature register */
-#define UART_OMAP_EFR 0x02
-
-#define UART_OMAP_EFR_ECB 0x10 /* Enhanced control bit */
-
-/* Mode definition register 1 */
-#define UART_OMAP_MDR1 0x08
-
-/*
- * These are the definitions for the MDR1 register
- */
-#define UART_OMAP_MDR1_16X_MODE 0x00 /* UART 16x mode */
-#define UART_OMAP_MDR1_DISABLE 0x07 /* Disable (default state) */
-
-/* Supplementary control register */
-#define UART_OMAP_SCR 0x10
-
-/* SCR register bitmasks */
-#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
-
-/* System configuration register */
-#define OMAP_UART_SYSC_DEF_CONF 0x0d /* autoidle mode, wakeup is enabled */
-
#endif /* __XEN_8250_UART_H__ */
/*