}
int xc_hvm_inject_trap(
- xc_interface *xch, domid_t dom, int vcpu, uint32_t trap, uint32_t error_code,
+ xc_interface *xch, domid_t dom, int vcpu, uint32_t vector,
+ uint32_t type, uint32_t error_code, uint32_t inslen,
uint64_t cr2)
{
DECLARE_HYPERCALL;
arg->domid = dom;
arg->vcpuid = vcpu;
- arg->trap = trap;
+ arg->vector = vector;
+ arg->type = type;
arg->error_code = error_code;
+ arg->inslen = inslen;
arg->cr2 = cr2;
hypercall.op = __HYPERVISOR_hvm_op;
* resumes.
*/
int xc_hvm_inject_trap(
- xc_interface *xch, domid_t dom, int vcpu, uint32_t trap, uint32_t error_code,
+ xc_interface *xch, domid_t dom, int vcpu, uint32_t vector,
+ uint32_t type, uint32_t error_code, uint32_t inslen,
uint64_t cr2);
/*
req.vcpu_id);
/* Reinject */
- rc = xc_hvm_inject_trap(xch, domain_id, req.vcpu_id, 3, -1, 0);
+ rc = xc_hvm_inject_trap(
+ xch, domain_id, req.vcpu_id, 3,
+ HVMOP_TRAP_hw_exc, -1, 0, 0);
if (rc < 0)
{
ERROR("Error %d injecting int3\n", rc);
rc = -EBUSY;
else
{
- v->arch.hvm_vcpu.inject_trap.vector = tr.trap;
+ v->arch.hvm_vcpu.inject_trap.vector = tr.vector;
+ v->arch.hvm_vcpu.inject_trap.type = tr.type;
v->arch.hvm_vcpu.inject_trap.error_code = tr.error_code;
+ v->arch.hvm_vcpu.inject_trap.inslen = tr.inslen;
v->arch.hvm_vcpu.inject_trap.cr2 = tr.cr2;
}
int vector;
unsigned int type; /* X86_EVENTTYPE_* */
int error_code; /* HVM_DELIVER_NO_ERROR_CODE if n/a */
- unsigned long cr2; /* Only for TRAP_page_fault h/w exception */
int inslen; /* Instruction length */
+ unsigned long cr2; /* Only for TRAP_page_fault h/w exception */
};
/*
* Intel VMX: {VM_ENTRY,VM_EXIT,IDT_VECTORING}_INTR_INFO[10:8]
* AMD SVM: eventinj[10:8] and exitintinfo[10:8] (types 0-4 only)
*/
-#define X86_EVENTTYPE_EXT_INTR 0 /* external interrupt */
-#define X86_EVENTTYPE_NMI 2 /* NMI */
-#define X86_EVENTTYPE_HW_EXCEPTION 3 /* hardware exception */
-#define X86_EVENTTYPE_SW_INTERRUPT 4 /* software interrupt */
-#define X86_EVENTTYPE_PRI_SW_EXCEPTION 5 /* privileged software exception */
-#define X86_EVENTTYPE_SW_EXCEPTION 6 /* software exception */
+#define X86_EVENTTYPE_EXT_INTR 0 /* external interrupt */
+#define X86_EVENTTYPE_NMI 2 /* NMI */
+#define X86_EVENTTYPE_HW_EXCEPTION 3 /* hardware exception */
+#define X86_EVENTTYPE_SW_INTERRUPT 4 /* software interrupt (CD nn) */
+#define X86_EVENTTYPE_PRI_SW_EXCEPTION 5 /* ICEBP (F1) */
+#define X86_EVENTTYPE_SW_EXCEPTION 6 /* INT3 (CC), INTO (CE) */
int hvm_event_needs_reinjection(uint8_t type, uint8_t vector);
domid_t domid;
/* VCPU */
uint32_t vcpuid;
- /* Trap number */
- uint32_t trap;
- /* Error code, or -1 to skip */
+ /* Vector number */
+ uint32_t vector;
+ /* Trap type (HVMOP_TRAP_*) */
+ uint32_t type;
+/* NB. This enumeration precisely matches hvm.h:X86_EVENTTYPE_* */
+# define HVMOP_TRAP_ext_int 0 /* external interrupt */
+# define HVMOP_TRAP_nmi 2 /* nmi */
+# define HVMOP_TRAP_hw_exc 3 /* hardware exception */
+# define HVMOP_TRAP_sw_int 4 /* software interrupt (CD nn) */
+# define HVMOP_TRAP_pri_sw_exc 5 /* ICEBP (F1) */
+# define HVMOP_TRAP_sw_exc 6 /* INT3 (CC), INTO (CE) */
+ /* Error code, or ~0u to skip */
uint32_t error_code;
+ /* Intruction length */
+ uint32_t inslen;
/* CR2 for page faults */
uint64_aligned_t cr2;
};