drm/amd/display: Lock all enabled otg pipes even with no planes

[WHY]
On DCN32 we support dynamic ODM even when OTG is blanked. When ODM
configuration is dynamically changed and the OTG is on blank pattern,
we will need to reprogram OPP's test pattern based on new ODM
configuration. Therefore we need to lock the OTG pipe to avoid temporary
corruption when we are reprogramming OPP blank patterns.

[HOW]
Add a new interdependent update lock implementation to lock all enabled
OTG pipes even when there is no plane on the OTG for DCN32.

Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
index b890db0bfc46b22d8ae6a39eebf851b16d10946d..c0b526cf178654f1c9fedb95e08831e965a911a7 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
@@ -1785,3 +1785,26 @@ void dcn32_prepare_bandwidth(struct dc *dc,
                context->bw_ctx.bw.dcn.clk.p_state_change_support = p_state_change_support;
        }
 }
+
+void dcn32_interdependent_update_lock(struct dc *dc,
+               struct dc_state *context, bool lock)
+{
+       unsigned int i;
+       struct pipe_ctx *pipe;
+       struct timing_generator *tg;
+
+       for (i = 0; i < dc->res_pool->pipe_count; i++) {
+               pipe = &context->res_ctx.pipe_ctx[i];
+               tg = pipe->stream_res.tg;
+
+               if (!resource_is_pipe_type(pipe, OTG_MASTER) ||
+                               !tg->funcs->is_tg_enabled(tg) ||
+                               dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM)
+                       continue;
+
+               if (lock)
+                       dc->hwss.pipe_control_lock(dc, pipe, true);
+               else
+                       dc->hwss.pipe_control_lock(dc, pipe, false);
+       }
+}

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h
index 069e20bc87c0a75af028168253219fc9343b1af3..f55c11fc56ec7a7a3d86cff32269a89fb6c5a3d5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h
@@ -129,4 +129,6 @@ bool dcn32_is_pipe_topology_transition_seamless(struct dc *dc,
 void dcn32_prepare_bandwidth(struct dc *dc,
        struct dc_state *context);
 
+void dcn32_interdependent_update_lock(struct dc *dc,
+               struct dc_state *context, bool lock);
 #endif /* __DC_HWSS_DCN32_H__ */

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c
index 2b073123d3ede2eb16ae766af9a285511fc6e8ea..67d661dbd5b7c7c20673424102b139c8df47d9be 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c
@@ -58,7 +58,7 @@ static const struct hw_sequencer_funcs dcn32_funcs = {
        .disable_plane = dcn20_disable_plane,
        .disable_pixel_data = dcn20_disable_pixel_data,
        .pipe_control_lock = dcn20_pipe_control_lock,
-       .interdependent_update_lock = dcn10_lock_all_pipes,
+       .interdependent_update_lock = dcn32_interdependent_update_lock,
        .cursor_lock = dcn10_cursor_lock,
        .prepare_bandwidth = dcn32_prepare_bandwidth,
        .optimize_bandwidth = dcn20_optimize_bandwidth,