clk: qcom: gpucc-sm6375: Configure CX_GDSC disable wait value

Configure the disable wait value on the CX GDSC to ensure we don't get
any undefined behavior. This was omitted when first adding the driver.

Fixes: 8397e24278b3 ("clk: qcom: Add GPU clock controller driver for SM6375")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230329140135.2178957-1-konrad.dybcio@linaro.org

diff --git a/drivers/clk/qcom/gpucc-sm6375.c b/drivers/clk/qcom/gpucc-sm6375.c
index d8f4c4b59f1b1db8027cd21178cb756843138ab0..d3620344a00968b9471ef1306f51f275946a6f4f 100644 (file)
--- a/drivers/clk/qcom/gpucc-sm6375.c
+++ b/drivers/clk/qcom/gpucc-sm6375.c
@@ -358,6 +358,7 @@ static struct clk_branch gpucc_sleep_clk = {
 static struct gdsc gpu_cx_gdsc = {
        .gdscr = 0x106c,
        .gds_hw_ctrl = 0x1540,
+       .clk_dis_wait_val = 8,
        .pd = {
                .name = "gpu_cx_gdsc",
        },