]> xenbits.xensource.com Git - people/julieng/linux-arm.git/commitdiff
drm/mediatek: adjust ddp clock control flow
authorYongqiang Niu <yongqiang.niu@mediatek.com>
Wed, 27 Mar 2019 06:19:18 +0000 (14:19 +0800)
committerCK Hu <ck.hu@mediatek.com>
Wed, 29 May 2019 06:54:38 +0000 (14:54 +0800)
display hardware clock will not unprepare when
crtc is disable, until crtc is destroyed.
with this patch, hard clock will disable and unprepare
at the same time.

Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
drivers/gpu/drm/mediatek/mtk_drm_crtc.c

index acad088173dab2ccaedba044f116570af8d35e3d..529b8a4af71581c61b60be050a334105eb363d39 100644 (file)
@@ -98,10 +98,6 @@ static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc)
 static void mtk_drm_crtc_destroy(struct drm_crtc *crtc)
 {
        struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
-       int i;
-
-       for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
-               clk_unprepare(mtk_crtc->ddp_comp[i]->clk);
 
        mtk_disp_mutex_put(mtk_crtc->mutex);
 
@@ -194,7 +190,7 @@ static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc)
 
        DRM_DEBUG_DRIVER("%s\n", __func__);
        for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
-               ret = clk_enable(mtk_crtc->ddp_comp[i]->clk);
+               ret = clk_prepare_enable(mtk_crtc->ddp_comp[i]->clk);
                if (ret) {
                        DRM_ERROR("Failed to enable clock %d: %d\n", i, ret);
                        goto err;
@@ -204,7 +200,7 @@ static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc)
        return 0;
 err:
        while (--i >= 0)
-               clk_disable(mtk_crtc->ddp_comp[i]->clk);
+               clk_disable_unprepare(mtk_crtc->ddp_comp[i]->clk);
        return ret;
 }
 
@@ -214,7 +210,7 @@ static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc)
 
        DRM_DEBUG_DRIVER("%s\n", __func__);
        for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
-               clk_disable(mtk_crtc->ddp_comp[i]->clk);
+               clk_disable_unprepare(mtk_crtc->ddp_comp[i]->clk);
 }
 
 static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
@@ -585,15 +581,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
                if (!comp) {
                        dev_err(dev, "Component %pOF not initialized\n", node);
                        ret = -ENODEV;
-                       goto unprepare;
-               }
-
-               ret = clk_prepare(comp->clk);
-               if (ret) {
-                       dev_err(dev,
-                               "Failed to prepare clock for component %pOF: %d\n",
-                               node, ret);
-                       goto unprepare;
+                       return ret;
                }
 
                mtk_crtc->ddp_comp[i] = comp;
@@ -611,23 +599,17 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
                ret = mtk_plane_init(drm_dev, &mtk_crtc->planes[zpos],
                                     BIT(pipe), type);
                if (ret)
-                       goto unprepare;
+                       return ret;
        }
 
        ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, &mtk_crtc->planes[0],
                                mtk_crtc->layer_nr > 1 ? &mtk_crtc->planes[1] :
                                NULL, pipe);
        if (ret < 0)
-               goto unprepare;
+               return ret;
        drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE);
        drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, MTK_LUT_SIZE);
        priv->num_pipes++;
 
        return 0;
-
-unprepare:
-       while (--i >= 0)
-               clk_unprepare(mtk_crtc->ddp_comp[i]->clk);
-
-       return ret;
 }