x86/AMD: work around erratum 793 for 32-bit

The original change went into a 64-bit only code section, thus leaving
the issue unfixed on 32-bit. Re-order code to address this.

This is part of CVE-2013-6885 / XSA-82.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Ian Campbell <Ian.Campbell@citrix.com>

diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index 54ca33c6543290f59b3afd6ccf291e4709f8391b..e1190efb5afca2f58cc4dec36a53d7a716499bc7 100644 (file)
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -649,6 +649,18 @@ static void __devinit init_amd(struct cpuinfo_x86 *c)
                       "*** Pass \"allow_unsafe\" if you're trusting"
                       " all your (PV) guest kernels. ***\n");
 
+       /* AMD CPUs do not support SYSENTER outside of legacy mode. */
+       clear_bit(X86_FEATURE_SEP, c->x86_capability);
+
+       if (c->x86 == 0x10) {
+               /* do this for boot cpu */
+               if (c == &boot_cpu_data)
+                       check_enable_amd_mmconf_dmi();
+
+               fam10h_check_enable_mmcfg();
+       }
+#endif
+
        if (c->x86 == 0x16 && c->x86_model <= 0xf) {
                rdmsrl(MSR_AMD64_LS_CFG, value);
                if (!(value & (1 << 15))) {
@@ -663,18 +675,6 @@ static void __devinit init_amd(struct cpuinfo_x86 *c)
                }
        }
 
-       /* AMD CPUs do not support SYSENTER outside of legacy mode. */
-       clear_bit(X86_FEATURE_SEP, c->x86_capability);
-
-       if (c->x86 == 0x10) {
-               /* do this for boot cpu */
-               if (c == &boot_cpu_data)
-                       check_enable_amd_mmconf_dmi();
-
-               fam10h_check_enable_mmcfg();
-       }
-#endif
-
        if (c->x86 == 0x10) {
                /*
                 * On family 10h BIOS may not have properly enabled WC+