xen: arm: Implement OSDLR_EL1 trap as RAZ/WO.

I'm not sure why this wasn't added at the same time as the other
debug registers.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Acked-by: Julien Grall <julien.grall@linaro.org>

diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index 9bc3198398dbdc3875f330890ba0275409d9b4b9..994b654846d7ab5c1ce65db8ed69190aa63379e1 100644 (file)
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -1596,9 +1596,11 @@ static void do_sysreg(struct cpu_user_regs *regs,
     /* - Breakpoints */
     HSR_SYSREG_DBG_CASES(DBGBVR):
     HSR_SYSREG_DBG_CASES(DBGBCR):
-    /* -  Watchpoints */
+    /* - Watchpoints */
     HSR_SYSREG_DBG_CASES(DBGWVR):
     HSR_SYSREG_DBG_CASES(DBGWCR):
+    /* - Double Lock Register */
+    case HSR_SYSREG_OSDLR_EL1:
         if ( hsr.sysreg.read )
             *x = 0;
         /* else: write ignored */

diff --git a/xen/include/asm-arm/sysregs.h b/xen/include/asm-arm/sysregs.h
index 4a4de342b31bc1aa432c8f03fc15bf2594d43be4..b00871c18f49b8d026e2f40f9f7d3e03efcb4067 100644 (file)
--- a/xen/include/asm-arm/sysregs.h
+++ b/xen/include/asm-arm/sysregs.h
@@ -42,6 +42,7 @@
 
 #define HSR_SYSREG_MDSCR_EL1      HSR_SYSREG(2,0,c0,c2,2)
 #define HSR_SYSREG_OSLAR_EL1      HSR_SYSREG(2,0,c1,c0,4)
+#define HSR_SYSREG_OSDLR_EL1      HSR_SYSREG(2,0,c1,c3,4)
 
 #define HSR_SYSREG_DBGBVRn_EL1(n) HSR_SYSREG(2,0,c0,c##n,4)
 #define HSR_SYSREG_DBGBCRn_EL1(n) HSR_SYSREG(2,0,c0,c##n,5)