lr_reg->virq = (lrv >> GICH_V2_LR_VIRTUAL_SHIFT) & GICH_V2_LR_VIRTUAL_MASK;
lr_reg->priority = (lrv >> GICH_V2_LR_PRIORITY_SHIFT) & GICH_V2_LR_PRIORITY_MASK;
lr_reg->state = (lrv >> GICH_V2_LR_STATE_SHIFT) & GICH_V2_LR_STATE_MASK;
- lr_reg->hw_status = (lrv >> GICH_V2_LR_HW_SHIFT) & GICH_V2_LR_HW_MASK;
+ lr_reg->hw_status = lrv & GICH_V2_LR_HW;
}
static void gicv2_write_lr(int lr, const struct gic_lr *lr_reg)
((uint32_t)(lr_reg->priority & GICH_V2_LR_PRIORITY_MASK)
<< GICH_V2_LR_PRIORITY_SHIFT) |
((uint32_t)(lr_reg->state & GICH_V2_LR_STATE_MASK)
- << GICH_V2_LR_STATE_SHIFT) |
- ((uint32_t)(lr_reg->hw_status & GICH_V2_LR_HW_MASK)
- << GICH_V2_LR_HW_SHIFT));
+ << GICH_V2_LR_STATE_SHIFT) );
+
+ if ( lr_reg->hw_status )
+ lrv |= GICH_V2_LR_HW;
writel_gich(lrv, GICH_LR + lr * 4);
}
lr_reg->priority = (lrv >> ICH_LR_PRIORITY_SHIFT) & ICH_LR_PRIORITY_MASK;
lr_reg->state = (lrv >> ICH_LR_STATE_SHIFT) & ICH_LR_STATE_MASK;
- lr_reg->hw_status = (lrv >> ICH_LR_HW_SHIFT) & ICH_LR_HW_MASK;
+ lr_reg->hw_status = lrv & ICH_LR_HW;
}
static void gicv3_write_lr(int lr_reg, const struct gic_lr *lr)
lrv = ( ((u64)(lr->pirq & ICH_LR_PHYSICAL_MASK) << ICH_LR_PHYSICAL_SHIFT)|
((u64)(lr->virq & ICH_LR_VIRTUAL_MASK) << ICH_LR_VIRTUAL_SHIFT) |
((u64)(lr->priority & ICH_LR_PRIORITY_MASK) << ICH_LR_PRIORITY_SHIFT)|
- ((u64)(lr->state & ICH_LR_STATE_MASK) << ICH_LR_STATE_SHIFT) |
- ((u64)(lr->hw_status & ICH_LR_HW_MASK) << ICH_LR_HW_SHIFT) );
+ ((u64)(lr->state & ICH_LR_STATE_MASK) << ICH_LR_STATE_SHIFT) );
+
+ if ( lr->hw_status )
+ lrv |= ICH_LR_HW;
/*
* When the guest is using vGICv3, all the IRQs are Group 1. Group 0