return false;
if ((rc = rdmsr_safe(MSR_INTEL_PLATFORM_INFO, val)) == 0)
- raw_msr_policy.plaform_info.cpuid_faulting =
+ raw_msr_policy.platform_info.cpuid_faulting =
val & MSR_PLATFORM_INFO_CPUID_FAULTING;
if (rc ||
/* 0x000000ce MSR_INTEL_PLATFORM_INFO */
/* probe_cpuid_faulting() sanity checks presence of MISC_FEATURES_ENABLES */
- mp->plaform_info.cpuid_faulting = cpu_has_cpuid_faulting;
+ mp->platform_info.cpuid_faulting = cpu_has_cpuid_faulting;
}
static void __init calculate_hvm_max_policy(void)
*mp = host_msr_policy;
/* It's always possible to emulate CPUID faulting for HVM guests */
- mp->plaform_info.cpuid_faulting = true;
+ mp->platform_info.cpuid_faulting = true;
}
static void __init calculate_pv_max_policy(void)
/* See comment in intel_ctxt_switch_levelling() */
if ( is_control_domain(d) )
- mp->plaform_info.cpuid_faulting = false;
+ mp->platform_info.cpuid_faulting = false;
d->arch.msr = mp;
break;
case MSR_INTEL_PLATFORM_INFO:
- *val = mp->plaform_info.raw;
+ *val = mp->platform_info.raw;
break;
case MSR_ARCH_CAPABILITIES:
bool old_cpuid_faulting = msrs->misc_features_enables.cpuid_faulting;
rsvd = ~0ull;
- if ( mp->plaform_info.cpuid_faulting )
+ if ( mp->platform_info.cpuid_faulting )
rsvd &= ~MSR_MISC_FEATURES_CPUID_FAULTING;
if ( val & rsvd )
return ret; \
})
- COPY_MSR(MSR_INTEL_PLATFORM_INFO, p->plaform_info.raw);
+ COPY_MSR(MSR_INTEL_PLATFORM_INFO, p->platform_info.raw);
#undef COPY_MSR
p->field = data.val; \
})
- case MSR_INTEL_PLATFORM_INFO: ASSIGN(plaform_info.raw); break;
+ case MSR_INTEL_PLATFORM_INFO: ASSIGN(platform_info.raw); break;
#undef ASSIGN